SLDS272 September   2024 DRV81620-Q1

ADVANCE INFORMATION  

1.   1
2. 1 Features
3. 2 Applications
4. 3 Description
5. 4 Device Comparison
6. 5 Pin Configuration and Functions
7. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 Electrical Characteristics
      1. 6.5.1 SPI Timing Requirements
8. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1 Control Pins
         1. 7.3.1.1 Input Pins
         2. 7.3.1.2 nSLEEP Pin
      2. 7.3.2 Power Supply
         1. 7.3.2.1 Modes of Operation
            1. 7.3.2.1.1 Power-up
            2. 7.3.2.1.2 Sleep mode
            3. 7.3.2.1.3 Idle mode
            4. 7.3.2.1.4 Active mode
            5. 7.3.2.1.5 Limp Home mode
         2. 7.3.2.2 Reset condition
      3. 7.3.3 Power Stage
         1. 7.3.3.1 Switching Resistive Loads
         2. 7.3.3.2 Inductive Output Clamp
         3. 7.3.3.3 Maximum Load Inductance
         4. 7.3.3.4 Reverse Current Behavior
         5. 7.3.3.5 Switching Channels in parallel
         6. 7.3.3.6 Bulb Inrush Mode (BIM)
         7. 7.3.3.7 Integrated PWM Generator
      4. 7.3.4 Protection and Diagnostics
         1. 7.3.4.1 Undervoltage on VM
         2. 7.3.4.2 Overcurrent Protection
         3. 7.3.4.3 Over Temperature Protection
         4. 7.3.4.4 Over Temperature Warning
         5. 7.3.4.5 Over Temperature and Overcurrent Protection in Limp Home mode
         6. 7.3.4.6 Reverse Polarity Protection
         7. 7.3.4.7 Over Voltage Protection
         8. 7.3.4.8 Output Status Monitor
         9. 7.3.4.9 Open Load Detection in ON State
            1. 7.3.4.9.1 Open Load at ON - direct channel diagnosis
            2. 7.3.4.9.2 Open Load at ON - diagnosis loop
            3. 7.3.4.9.3 OLON bit
      5. 7.3.5 SPI Communication
         1. 7.3.5.1 SPI Signal Description
            1. 7.3.5.1.1 Chip Select (nSCS)
               1. 7.3.5.1.1.1 Logic high to logic low Transition
               2. 7.3.5.1.1.2 Logic low to logic high Transition
            2. 7.3.5.1.2 Serial Clock (SCLK)
            3. 7.3.5.1.3 Serial Input (SDI)
            4. 7.3.5.1.4 Serial Output (SDO)
         2. 7.3.5.2 Daisy Chain Capability
         3. 7.3.5.3 SPI Protocol
         4. 7.3.5.4 SPI Registers
            1. 7.3.5.4.1  Standard Diagnosis Register
            2. 7.3.5.4.2  Output control register
            3. 7.3.5.4.3  Bulb Inrush Mode Register
            4. 7.3.5.4.4  Input 0 Mapping Register
            5. 7.3.5.4.5  Input 1 Mapping Register
            6. 7.3.5.4.6  Input Status Monitor Register
            7. 7.3.5.4.7  Open Load Current Control Register
            8. 7.3.5.4.8  Output Status Monitor Register
            9. 7.3.5.4.9  Open Load at ON Register
            10. 7.3.5.4.10 EN_OLON Register
            11. 7.3.5.4.11 Configuration Register
            12. 7.3.5.4.12 Output Clear Latch Register
            13. 7.3.5.4.13 FPWM Register
            14. 7.3.5.4.14 PWM0 Configuration Register
            15. 7.3.5.4.15 PWM1 Configuration Register
            16. 7.3.5.4.16 PWM_OUT Register
            17. 7.3.5.4.17 MAP_PWM Register
            18. 7.3.5.4.18 Configuration 2 Register
9. 8 Application and Implementation
   1. 8.1 Application Information
      1. 8.1.1 Suggested External Components
   2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
      2. 8.2.2 Package Footprint Compatibility
10. 9 Revision History
11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information