SLDS272 September   2024 DRV81620-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 SPI Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Pins
        1. 7.3.1.1 Input Pins
        2. 7.3.1.2 nSLEEP Pin
      2. 7.3.2 Power Supply
        1. 7.3.2.1 Modes of Operation
          1. 7.3.2.1.1 Power-up
          2. 7.3.2.1.2 Sleep mode
          3. 7.3.2.1.3 Idle mode
          4. 7.3.2.1.4 Active mode
          5. 7.3.2.1.5 Limp Home mode
        2. 7.3.2.2 Reset condition
      3. 7.3.3 Power Stage
        1. 7.3.3.1 Switching Resistive Loads
        2. 7.3.3.2 Inductive Output Clamp
        3. 7.3.3.3 Maximum Load Inductance
        4. 7.3.3.4 Reverse Current Behavior
        5. 7.3.3.5 Switching Channels in parallel
        6. 7.3.3.6 Bulb Inrush Mode (BIM)
        7. 7.3.3.7 Integrated PWM Generator
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Undervoltage on VM
        2. 7.3.4.2 Overcurrent Protection
        3. 7.3.4.3 Over Temperature Protection
        4. 7.3.4.4 Over Temperature Warning
        5. 7.3.4.5 Over Temperature and Overcurrent Protection in Limp Home mode
        6. 7.3.4.6 Reverse Polarity Protection
        7. 7.3.4.7 Over Voltage Protection
        8. 7.3.4.8 Output Status Monitor
        9. 7.3.4.9 Open Load Detection in ON State
          1. 7.3.4.9.1 Open Load at ON - direct channel diagnosis
          2. 7.3.4.9.2 Open Load at ON - diagnosis loop
          3. 7.3.4.9.3 OLON bit
      5. 7.3.5 SPI Communication
        1. 7.3.5.1 SPI Signal Description
          1. 7.3.5.1.1 Chip Select (nSCS)
            1. 7.3.5.1.1.1 Logic high to logic low Transition
            2. 7.3.5.1.1.2 Logic low to logic high Transition
          2. 7.3.5.1.2 Serial Clock (SCLK)
          3. 7.3.5.1.3 Serial Input (SDI)
          4. 7.3.5.1.4 Serial Output (SDO)
        2. 7.3.5.2 Daisy Chain Capability
        3. 7.3.5.3 SPI Protocol
        4. 7.3.5.4 SPI Registers
          1. 7.3.5.4.1  Standard Diagnosis Register
          2. 7.3.5.4.2  Output control register
          3. 7.3.5.4.3  Bulb Inrush Mode Register
          4. 7.3.5.4.4  Input 0 Mapping Register
          5. 7.3.5.4.5  Input 1 Mapping Register
          6. 7.3.5.4.6  Input Status Monitor Register
          7. 7.3.5.4.7  Open Load Current Control Register
          8. 7.3.5.4.8  Output Status Monitor Register
          9. 7.3.5.4.9  Open Load at ON Register
          10. 7.3.5.4.10 EN_OLON Register
          11. 7.3.5.4.11 Configuration Register
          12. 7.3.5.4.12 Output Clear Latch Register
          13. 7.3.5.4.13 FPWM Register
          14. 7.3.5.4.14 PWM0 Configuration Register
          15. 7.3.5.4.15 PWM1 Configuration Register
          16. 7.3.5.4.16 PWM_OUT Register
          17. 7.3.5.4.17 MAP_PWM Register
          18. 7.3.5.4.18 Configuration 2 Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Suggested External Components
    2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
      2. 8.2.2 Package Footprint Compatibility
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.1 Overview

The DRV81620-Q1 is an eight channel low-side and high-side switch providing integrated protection and diagnostic functions. The output stages incorporate two high-side and six auto-configurable high-side or low-side switches (typical RDS(ON) at TJ = 25 °C is 630 mΩ). The power transistors are built by N-channel MOSFETs with one charge pump for auto-configurable and high-side channels.

The auto-configurable switches can be utilized in high-side or low-side configuration by connecting the load accordingly. Protection and diagnosis functions adjust automatically to the hardware configuration. Driving a load from high-side offers the possibility to perform Open Load at ON diagnosis.

The 16-bit serial peripheral interface (SPI) is utilized to control and diagnose the device and the loads. The SPI interface provides daisy chain support in order to connect multiple devices (also devices with 8 bit SPI) in one SPI chain by using the same microcontroller pins. The SPI feature, including the possibility to program the device, is available only when the digital power supply is present.

The device is designed for low supply voltage operation. It can keep its state at low battery voltage (VM ≥ 3 V).

The device is equipped with two input pins that are connected to two configurable outputs, making them controllable even when the digital supply voltage is not available. With the Input Mapping feature, it is possible to connect the input pins to different outputs, or assign more outputs to the same input pin. In this case more channels can be controlled with one input signal.

In Limp Home mode, the input pins are directly routed to channels 2 and 3. When nSLEEP pin is logic low, it is possible to activate the two channels using the input pins independently from the presence of the digital supply voltage.

The device provides diagnosis of the load via Open Load in ON and OFF state, and short circuit detection. For Open Load in OFF state detection, an internal current source IOL can be activated via SPI.

Each output stage is protected against short circuit. In case of Overcurrent, the affected channel switches OFF when the Overcurrent Detection threshold is reached and can be reactivated via SPI. In Limp Home mode operation, the channels connected to an input pin set to logic high restart automatically after Output Restart time is elapsed. Temperature sensors are available for each channel to protect the device against Over Temperature.

Table 7-1 Product Summary

Parameter

Symbol

Values
Analog supply voltage

VM

3.0 V to 40 V

Digital supply voltage

VDD

3.0 V to 5.5 V
Minimum overvoltage protection

VM_AZ

45 V

Maximum on-state resistance at TJ = 150 °C

RDS(ON)

1.3 Ω
Nominal load current (TA = 85 °C, all channels)

IL_NOM

330 mA
Maximum Energy dissipation - repetitive

EAR

10 mJ @ IL_EAR = 220 mA
Minimum Drain to Source clamping voltage

VDS_CL

44 V

Maximum Source to ground output clamping voltage

VOUT_CL

-19 V

Maximum overload switch OFF threshold

IL_OVL0

1.9 A or 2.7 A

Maximum total quiescent current at TJ ≤ 85 °C

ISLEEP

6.5 μA

Maximum SPI clock frequency

fSCLK

5 MHz
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