ZHCS138C August   2011  – March 2016 DRV8302

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Gate Timing and Protection Characteristics
    7. 6.7 Current Shunt Amplifier Characteristics
    8. 6.8 Buck Converter Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Function Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three-Phase Gate Driver
      2. 7.3.2 Current Shunt Amplifiers
      3. 7.3.3 Buck Converter
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Overcurrent Protection (OCP) and Reporting
          1. 7.3.4.1.1 Current Limit Mode (M_OC = LOW)
          2. 7.3.4.1.2 OC Latch Shutdown Mode
        2. 7.3.4.2 OC_ADJ
        3. 7.3.4.3 Undervoltage Protection (UVLO)
        4. 7.3.4.4 Overvoltage Protection (GVDD_OV)
        5. 7.3.4.5 Overtemperature Protection
        6. 7.3.4.6 Fault and Protection Handling
    4. 7.4 Device Functional Modes
      1. 7.4.1 EN_GATE
      2. 7.4.2 DTC
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Gate Driver Power Up Sequencing Errdata
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Average Current Load
        2. 8.2.2.2 Overcurrent Protection Setup
        3. 8.2.2.3 Sense Amplifier Setup
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档　
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DCA Package
56-Pin HTSSOP With PowerPAD™
Top View
DRV8302 po.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NO. NAME
1 RT_CLK I Resistor timing and external clock for buck regulator. Resistor should connect to GND (PowerPAD™) with very short trace to reduce the potential clock jitter due to noise.
2 COMP O Buck error amplifier output and input to the output switch current comparator.
3 VSENSE I Buck output voltage sense pin. Inverting node of error amplifier.
4 PWRGD I An open drain output with external pullup resistor required. Asserts low if buck output voltage is low due to thermal shutdown, dropout, overvoltage, or EN_BUCK shut down
5 nOCTW O Overcurrent and overtemperature warning indicator. This output is open drain with external pullup resistor required.
6 nFAULT O Fault report indicator. This output is open drain with external pullup resistor required.
7 DTC I Dead-time adjustment with external resistor to GND
8 M_PWM I Mode selection pin for PWM input configuration. If M_PWM = LOW, the device supports 6 independent PWM inputs. When M_PWM = HIGH, the device must be connected to ONLY 3 PWM input signals on INH_x. The complementary PWM signals for low side signaling will be internally generated from the high side inputs.
9 M_OC I Mode selection pin for over-current protection options. If M_OC = LOW, the gate driver will operate in a cycle-by-cycle current limiting mode. If M_OC = HIGH, the gate driver will shutdown the channel which detected an over-current event.
10 GAIN O Gain selection for integrated current shunt amplifiers. If GAIN = LOW, the internal current shunt amplifiers have a gain of 10V/V. If GAIN = HIGH, the current shunt amplifiers have a gain of 40V/V.
11 OC_ADJ I Overcurrent trip set pin. Apply a voltage on this pin to set the trip point for the internal overcurrent protection circuitry. A voltage divider from DVDD is recommended.
12 DC_CAL I When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset calibration can be done through external microcontroller.
13 GVDD P Internal gate driver voltage regulator. GVDD cap should connect to GND
14 CP1 P Charge pump pin 1, ceramic cap should be used between CP1 and CP2
15 CP2 P Charge pump pin 2, ceramic cap should be used between CP1 and CP2
16 EN_GATE I Enable gate driver and current shunt amplifiers. Control buck via EN_BUCK pin.
17 INH_A I PWM Input signal (high side), half-bridge A
18 INL_A I PWM Input signal (low side), half-bridge A
19 INH_B I PWM Input signal (high side), half-bridge B
20 INL_B I PWM Input signal (low side), half-bridge B
21 INH_C I PWM Input signal (high side), half-bridge C
22 INL_C I PWM Input signal (low side), half-bridge C
23 DVDD P Internal 3.3-V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified to drive external circuitry.
24 REF I Reference voltage to set output of shunt amplfiiers with a bias voltage which equals to half of the voltage set on this pin. Connect to ADC reference in microcontroller.
25 SO1 O Output of current amplifier 1
26 SO2 O Output of current amplifier 2
27 AVDD P Internal 6-V supply voltage, AVDD cap should connect to AGND. This is an output, but not specified to drive external circuitry.
28 AGND P Analog ground pin
29 PVDD1 P Power supply pin for gate driver and current shunt amplifier. PVDD1 is independent of buck power supply, PVDD2. PVDD1 cap should connect to GND
30 SP2 I Input of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best commom mode rejection.
31 SN2 I Input of current amplifier 2 (connecting to negative input of amplifier).
32 SP1 I Input of current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best commom mode rejection.
33 SN1 I Input of current amplifier 1 (connecting to negative input of amplifier).
34 SL_C I Low-Side MOSFET source connection, half-bridge C. Low-side VDS measured between this pin and SH_C.
35 GL_C O Gate drive output for Low-Side MOSFET, half-bridge C
36 SH_C I High-Side MOSFET source connection, half-bridge C. High-side VDS measured between this pin and PVDD1.
37 GH_C O Gate drive output for High-Side MOSFET, half-bridge C
38 BST_C P Bootstrap cap pin for half-bridge C
39 SL_B I Low-Side MOSFET source connection, half-bridge B. Low-side VDS measured between this pin and SH_B.
40 GL_B O Gate drive output for Low-Side MOSFET, half-bridge B
41 SH_B I High-Side MOSFET source connection, half-bridge B. High-side VDS measured between this pin and PVDD1.
42 GH_B O Gate drive output for High-Side MOSFET, half-bridge B
43 BST_B P Bootstrap cap pin for half-bridge B
44 SL_A I Low-Side MOSFET source connection, half-bridge A. Low-side VDS measured between this pin and SH_A.
45 GL_A O Gate drive output for Low-Side MOSFET, half-bridge A
46 SH_A I High-Side MOSFET source connection, half-bridge A. High-side VDS measured between this pin and PVDD1.
47 GH_A O Gate drive output for High-Side MOSFET, half-bridge A
48 BST_A P Bootstrap cap pin for half-bridge A
49 BIAS I Bias pin. Connect 1M-Ω resistor to GND, or 0.1 µF capacitor to GND.
50, 51 PH O The source of the internal high side MOSFET of buck converter
52 BST_BK P Bootstrap cap pin for buck converter
53, 54 PVDD2 P Power supply pin for buck converter, PVDD2 cap should connect to GND.
55 EN_BUCK I Enable buck converter. Internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors
56 SS_TR I Buck soft-start and tracking. An external capacitor connected to this pin sets the output rise time. Since the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. Cap should connect to GND
57 GND
(PWR_PAD)		 P GND pin. The exposed power pad must be electrically connected to ground plane through soldering to PCB for proper operation and connected to bottom side of PCB through vias for better thermal spreading.
(1) KEY: I =Input, O = Output, P = Power
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