7.3.8.3 MOSFET Overcurrent Protection (VDS_OCP)

To protect the system and external MOSFET from damage due to high current events, V_DS overcurrent monitors are implemented in the DRV8305-Q1.

The V_DS sensing is implemented for both the high-side and low-side MOSFETs through the pins below:

• High-side MOSFET: V_DS measured between VDRAIN and SHx pins.
• Low-side MOSFET: V_DS measured between SHx and SLx pins.

Based on the R_DS(on) of the power MOSFETs and the maximum allowed I_DS, a voltage threshold can be calculated, which when exceeded, triggers the V_DS overcurrent protection feature. The voltage threshold level (VDS_LEVEL) is programmable through the SPI VDS_LEVEL setting in register 0xC, bits D7-D3 and may be changed during gate driver operation if needed.

The V_DS overcurrent monitors implement adjustable blanking and deglitch times to prevent false trips due to switching voltage transients. The V_DS blanking time (t_BLANK) is inserted digitally and programmable through the SPI TBLANK setting in register 0x7, bits D3-D2. The t_BLANK time is inserted after each switch ON transistion (LOW to HIGH) of the output gate drivers is commanded. During the t_BLANK time, the V_DS comparators are not being monitored in order to prevent false trips when the MOSFET first turns ON. After the t_BLANK time expires the overcurrent monitors will begin actively watching for an overcurrent event.

The V_DS deglitch time (t_VDS) is inserted digitally and programmable through the SPI TVDS setting in register 0x7, bits D1-D0. The t_VDS time is a delay inserted after the V_DS sensing comparators have tripped to when the protection logic is informed that a V_DS event has occurred. If the overcurrent event does not persist through t_VDS delay then it will be ignored by the DRV8305-Q1.

Note that the dead time and blanking time are overlapping timers as shown in Figure 13.

Figure 13. V_DS Deglitch and Blank Diagram

The DRV8305-Q1 has three possible responses to a V_DS overcurrent event. This response is set through the SPI VDS_MODE setting in register 0xC, bits D2-D0.

• V_DS Latched Shutdown Mode:

When a V_DS overcurrent event occurs, the device will pull all gate drive outputs low in order to put all six external MOSFETs into high impedance mode. The fault will be reported on the nFAULT pin with the specific MOSFET in which the overcurrent event was detected in reported through the SPI status registers.

• V_DS Report Only Mode:

In this mode, the device will take no action related to the gate drivers. When the overcurrent event is detected the fault will be reported on the nFAULT pin with the specific MOSFET in which the overcurrent event was detected in reported through the SPI status registers. The gate drivers will continue to operate normally.

• V_DS Disabled Mode:

The device ignores all the V_DS overcurrent event detections and does not report them.