7.3.9.3 MCU Watchdog

The DRV8305-Q1 incorporates an MCU watchdog function to ensure that the external controller that is instructing the device is active and not in an unknown state. The MCU watchdog function may be enabled by writing a 1 to the WD_EN setting in the SPI register 0x9, bit D3. The default setting for the device is with the watchdog disabled. When the watchdog is enabled, an internal timer starts to countdown to the interval set by the WD_DLY setting in the SPI register 0x9, bits D6-D5. To restart the watchdog timer, the address 0x1 (status register) must be read by the controller within the interval set by the WD_DLY setting. If the watchdog timer is allowed to expire without the address 0x1 being read, a watchdog fault will be enabled.

Response to a watchdog fault is as follows:

• A latched fault occurs on the DRV8305-Q1 and the gate drivers are put into a safe state. An appropriate recovery sequence must then be performed.
• The PWRGD pin is taken low for 56 µs and then back high in order to reset the controller or indicate the watchdog fault.
• The nFAULT pin is asserted low, the WD_EN bit is cleared, and the WD_FAULT set high in register 0x3, bit D9.
• It is recommended to read the status registers as part of the recovery or power-up routine in order to determine whether a WD_FAULT had previously occurred.

Note that the watchdog fault results in a clearing of the WD_EN setting and it will have to be set again to resume watchdog functionality.