7.3.9.4 VREG Undervoltage (VREG_UV)

The DRV8305-Q1 has an undervoltage monitor on the VREG output regulator to ensure the external controller does not experience a brownout condition. The undervoltage monitor will signal a fault if the VREG output drops below a set threshold from its set point. The VREG output set point is configured for two different levels, 3.3 V or 5 V, depending on the DRV8305-Q1 device options (DRV83053Q and DRV83055Q). The VREG undervoltage level can be set through the SPI setting VREG_UV_LEVEL in register 0xB, bits D1-D0. The VREG undervoltage monitor can be disabled through the SPI setting DIS_VREG_PWRGD in register 0xB, bit D2.

Response to a VREG undervoltage fault is as follows:

• A latched fault occurs on the DRV8305-Q1 and the gate drivers are put into a safe state. An appropriate recovery sequence must then be performed.
• The PWRGD is taken low until the undervoltage condition is removed and for at least a minimum of 56 µs.
• The nFAULT pin is asserted low and the VREG_UV bit set high in register 0x3, bit D6.
• The fault can be cleared after the VREG undervoltage condition is removed with CLR_FLTS or an EN_GATE reset pulse.

Note that the VREG undervoltage monitor is disabled on the no regulator (VREF) device option (DRV8305NQ and DRV8305NE).