7.4.4 Sleep State

The sleep state can be entered by issuing a sleep command through the SLEEP bit in SPI register 0x9, bit D2 with the device in its standby state (EN_GATE = LOW). The device will not respond to a sleep command in its operating state. After the sleep command is received, the gate drivers and output regulator (VREG) will safely power down after a programmable delay set in the SPI register 0xB, bits D4-D3. The device can then only be enabled through the WAKE pin which is a high-voltage tolerant input pin. For the DRV8305-Q1 to be brought out of sleep, the WAKE pin must be at a voltage greater than 3 V. This allows the wake pin to be driven, for example, directly by the battery through a switch, through the inhibit pin (INH) on a standard LIN interface, or through standard digital logic. The WAKE pin will only react to a wake up command if PVDD > V_{PVDD_UVLO2}. After the DRV8305-Q1 is out of SLEEP mode, all activity on the WAKE pin is ignored. The sleep state erases all values in the SPI control registers and it is not recommended to write through SPI in the sleep state.