7.5.1.1 SPI

The DRV8305-Q1 uses a SPI to set device configurations, operating parameters, and read out diagnostic information. The DRV8305-Q1 SPI operates in slave mode. The SPI input data (SDI) word consists of a 16-bit word with a 5-bit command and 11 bits of data. The SPI output data (SDO) word consists of 11 bits of register data with the first 5 bits (MSB) as don't cares.

A valid frame must meet following conditions:

• CPOL (clock polarity) = 0 and CPHA (clock phase) = 1.
• SCLK must be low when nSCS transitions.
• Full 16 SCLK cycles.
• Data is always propagated on the rising edge of SCLK.
• Data is always captured on the falling edge of SCLK.
• MSB is shifted in and out first.
• When nSCS is high, SCLK and SDI are ignored and SDO is high impedance.
• nSCS should be taken high for at least 500 ns between frames.
• If the data sent to SDI is less than or greater than 16 bits it is considered a frame error and the data will be ignored.