ZHCSF68D May   2015  – July 2019 DRV8305-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements (Slave Mode Only)
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Integrated Three-Phase Gate Driver
      2. 7.3.2 INHx/INLx: Gate Driver Input Modes
      3. 7.3.3 VCPH Charge Pump: High-Side Gate Supply
      4. 7.3.4 VCP_LSD LDO: Low-Side Gate Supply
      5. 7.3.5 GHx/GLx: Half-Bridge Gate Drivers
        1. 7.3.5.1 Smart Gate Drive Architecture: IDRIVE
        2. 7.3.5.2 Smart Gate Drive Architecture: TDRIVE
        3. 7.3.5.3 CSAs: Current Shunt Amplifiers
      6. 7.3.6 DVDD and AVDD: Internal Voltage Regulators
      7. 7.3.7 VREG: Voltage Regulator Output
      8. 7.3.8 Protection Features
        1. 7.3.8.1 Fault and Warning Classification
        2. 7.3.8.2 MOSFET Shoot-Through Protection (TDRIVE)
        3. 7.3.8.3 MOSFET Overcurrent Protection (VDS_OCP)
          1. 7.3.8.3.1 MOSFET dV/dt Turn On Protection (TDRIVE)
          2. 7.3.8.3.2 MOSFET Gate Drive Protection (GDF)
        4. 7.3.8.4 Low-Side Source Monitors (SNS_OCP)
        5. 7.3.8.5 Fault and Warning Operating Modes
      9. 7.3.9 Undervoltage Warning (UVFL), Undervoltage Lockout (UVLO), and Overvoltage (OV) Protection
        1. 7.3.9.1 Overtemperature Warning (OTW) and Shutdown (OTSD) Protection
        2. 7.3.9.2 Reverse Supply Protection
        3. 7.3.9.3 MCU Watchdog
        4. 7.3.9.4 VREG Undervoltage (VREG_UV)
        5. 7.3.9.5 Latched Fault Reset Methods
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up Sequence
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
      4. 7.4.4 Sleep State
      5. 7.4.5 Limp Home or Fail Code Operation
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 SPI
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 Status Registers
        1. 7.6.1.1 Warning and Watchdog Reset (Address = 0x1)
          1. Table 10. Warning and Watchdog Reset Register Description
        2. 7.6.1.2 OV/VDS Faults (Address = 0x2)
          1. Table 11. OV/VDS Faults Register Description
        3. 7.6.1.3 IC Faults (Address = 0x3)
          1. Table 12. IC Faults Register Description
        4. 7.6.1.4 VGS Faults (Address = 0x4)
          1. Table 13. Gate Driver VGS Faults Register Description
      2. 7.6.2 Control Registers
        1. 7.6.2.1 HS Gate Drive Control (Address = 0x5)
          1. Table 14. HS Gate Driver Control Register Description
        2. 7.6.2.2 LS Gate Drive Control (Address = 0x6)
          1. Table 15. LS Gate Driver Control Register Description
        3. 7.6.2.3 Gate Drive Control (Address = 0x7)
          1. Table 16. Gate Drive Control Register Description
        4. 7.6.2.4 IC Operation (Address = 0x9)
          1. Table 17. IC Operation Register Description
        5. 7.6.2.5 Shunt Amplifier Control (Address = 0xA)
          1. Table 18. Shunt Amplifier Control Register Description
        6. 7.6.2.6 Voltage Regulator Control (Address = 0xB)
          1. Table 19. Voltage Regulator Control Register Description
        7. 7.6.2.7 VDS Sense Control (Address = 0xC)
          1. Table 20. VDS Sense Control Register Description
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Average Current
        2. 8.2.2.2 MOSFET Slew Rates
        3. 8.2.2.3 Overcurrent Protection
        4. 8.2.2.4 Current Sense Amplifiers
      3. 8.2.3 VREG Reference Voltage Input (DRV8305N)
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Consideration in Generator Mode
    2. 9.2 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

PHP Package
48-Pin HTQFP
Top View
DRV8305-Q1 po_slvsd12.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
EN_GATE 1 I Enable gate Enables the gate driver and current shunt amplifiers; internal pulldown.
INHA 2 I Bridge PWM input PWM input signal for bridge A high-side.
INLA 3 I Bridge PWM input PWM input signal for bridge A low-side.
INHB 4 I Bridge PWM input PWM input signal for bridge B high-side.
INLB 5 I Bridge PWM input PWM input signal for bridge B low-side.
INHC 6 I Bridge PWM input PWM input signal for bridge C high-side.
INLC 7 I Bridge PWM input PWM input signal for bridge C low-side.
nFAULT 8 OD Fault indicator When low indicates a fault has occurred; open drain; external pullup to MCU power supply needed (1 kΩ to 10 kΩ).
nSCS 9 I SPI chip select Select/enable for SPI; active low.
SDI 10 I SPI input SPI input signal.
SDO 11 O SPI output SPI output signal.
SCLK 12 I SPI clock SPI clock signal.
PWRGD 13 OD Power good VREG and MCU watchdog fault indication; open drain; external pullup to MCU power supply needed (1 kΩ to 10 kΩ).
GND 14, 45 P Device ground Must be connected to ground.
AVDD 15 P Analog regulator 5-V internal analog supply regulator; bypass to GND with a 6.3-V, 1-µF ceramic capacitor.
SO1 16 O Current amplifier output Output of current sense amplifier 1.
SO2 17 O Current amplifier output Output of current sense amplifier 2.
SO3 18 O Current amplifier output Output of current sense amplifier 3.
SN3 19 I Current amplifier negative input Negative input of current sense amplifier 3.
SP3 20 I Current amplifier positive input Positive input of current sense amplifier 3.
SN2 21 I Current amplifier negative input Negative input of current sense amplifier 2.
SP2 22 I Current amplifier positive input Positive input of current sense amplifier 2.
SN1 23 I Current amplifier negative input Negative input of current sense amplifier 1.
SP1 24 I Current amplifier positive input Positive input of current sense amplifier 1.
GLC 25 O Low-side gate driver Low-side gate driver output for half-bridge C.
SLC 26 I Low-side source connection Low-side source connection for half-bridge C.
SHC 27 I High-side source connection High-side source connection for half-bridge C.
GHC 28 O High-side gate driver High-side gate driver output for half-bridge C.
GHB 29 O High-side gate driver High-side gate driver output for half-bridge B.
SHB 30 I High-side source connection High-side source connection for half-bridge B.
SLB 31 I Low-side source connection Low-side source connection for half-bridge B.
GLB 32 O Low-side gate driver Low side gate driver output for half-bridge B.
GLA 33 O Low-side gate driver Low-side gate driver output for half-bridge A.
SLA 34 I Low-side source connection Low-side source connection for half-bridge A.
SHA 35 I High-side source connection High-side source connection for half-bridge A.
GHA 36 O High-side gate driver High-side gate driver output for half-bridge A.
VCP_LSD 37 P Low-side gate driver regulator Internal voltage regulator for low-side gate driver; connect 1-µF capacitor to GND.
VCPH 38 P High-side gate driver regulator Internal charge pump for high-side gate driver; connect 2.2-µF capacitor to PVDD.
CP2H 39 P Charge pump flying capacitor Flying capacitor for charge pump; connect 0.047-µF capacitor between CP2H and CP2L.
CP2L 40 P
PVDD 41 P Power supply Device power supply; minimum 4.7-µF ceramic capacitor to GND.
CP1L 42 P Charge pump flying capacitor Flying capacitor for charge pump; connect 0.047-µF capacitor between CP1H and CP1L.
CP1H 43 P
VDRAIN 44 P High-side drain High-side MOSFET drain connection; common for all three half bridges.
DVDD 46 P Digital regulator 3.3-V internal digital-supply regulator; bypass to GND with a 6.3-V, 1-µF ceramic capacitor.
WAKE 47 I Wake up from sleep control pin High voltage tolerant input pin to wake-up device from SLEEP; pin cannot be used to disable LDO; driver needs to be enabled and disabled separately.
VREG 48 P VREG/VREF Dual purpose pin based on part number; also supplies internal amplifier reference voltage and SDO pullup.
VREG: 3.3-V or 5-V, 50-mA LDO; connect 1-µF to GND.
VREF: Reference voltage; LDO disabled.
If PVDD voltage is lower than VREF pin voltage, there is a current path from VREF to PVDD through the internal LDO. The current must be limited to 50 mA by the system.
GND PPAD P Device ground Must be connected to ground.
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