10.1 Layout Guidelines

Use the following layout recommendations when designing a PCB for the DRV8305-Q1.

• The DVDD and AVDD 1-μF bypass capacitors should connect directly to the adjacent GND pin to minimize loop impedance for the bypass capacitor.
• The CP1 and CP2 0.047-μF flying capacitors should be placed directly next to the DRV8305-Q1 charge pump pins.
• The VCPH 2.2-μF and VCP_LSD 1-μF bypass capacitors should be placed close to their corresponding pins with a direct path back to the DRV8305-Q1 PVDD for VCPH and GND for VCP_LSD.
• The PVDD 4.7-μF bypass capacitor should be placed as close as possible to the DRV8305-Q1 PVDD supply pin.
• Use the proper footprint as shown in the mechanical drawing.
• Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the DRV8305-Q1 GH_X to the power MOSFET and returns through SH_X. The low-side loop is from the DRV8305-Q1 GL_X to the power MOSFET and returns through SL_X.
• The VDRAIN pin is used to sense the DRAIN voltage of the high-side MOSFETs for the V_DS overcurrent monitors. It should route through the 100-Ω series resistor directly to the MOSFET DRAIN, ideally at the midpoint of the half-bridge connections in order to get the most accurate sense point.