ZHCSE35 August   2015 DRV8305

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements (Slave Mode Only)
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three-Phase Gate Driver
      2. 7.3.2  Operating Modes
      3. 7.3.3  Charge Pump
      4. 7.3.4  Gate Driver Architecture
      5. 7.3.5  IDRIVE/TDRIVE
      6. 7.3.6  Slew Rate/Slope Control
      7. 7.3.7  Current Shunt Amplifiers
      8. 7.3.8  Internal Regulators (DVDD and AVDD)
      9. 7.3.9  Voltage Regulator Output for Driving External Loads (VREG)
      10. 7.3.10 Protection Features
        1. 7.3.10.1 Fault and Protection Handling
        2. 7.3.10.2 Shoothrough Protection
        3. 7.3.10.3 VDS Sensing - External FET Protection and Reporting (OC Event)
        4. 7.3.10.4 Low-Side Source Monitoring (SNS_OCP)
      11. 7.3.11 Undervoltage Reporting and Undervoltage Lockout (UVLO) Protection
        1. 7.3.11.1 Battery Overvoltage Protection (PVDD_OV)
        2. 7.3.11.2 Charge Pump Overvoltage Protection (VCPH_OV/VCP_LSD_OV)
        3. 7.3.11.3 Overtemperature (OT) Warning and Protection
        4. 7.3.11.4 dV/dt Protection
        5. 7.3.11.5 VGS Protection
        6. 7.3.11.6 Gate Driver Faults
        7. 7.3.11.7 Reverse Battery Protection
        8. 7.3.11.8 MCU Watchdog
      12. 7.3.12 Pin Control Functions
        1. 7.3.12.1 EN_GATE
        2. 7.3.12.2 SPI Pins
      13. 7.3.13 Fault / Warning Classes and Recovery
        1. 7.3.13.1 Reg 09h CLR_FLTS
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Up and Operating States Hardware Configuration for VREG/VREF
        1. 7.4.1.1 POWER Up
        2. 7.4.1.2 STANDBY State
        3. 7.4.1.3 OPERATING State
        4. 7.4.1.4 SLEEP State
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 SPI
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 Read / Write Bit
      2. 7.6.2 Status Registers
      3. 7.6.3 0x1 Warning and Watchdog Reset
      4. 7.6.4 0x2 OV/VDS Faults
      5. 7.6.5 0x3 IC Faults
      6. 7.6.6 0x4 Gate Driver VGS Faults
      7. 7.6.7 Control Registers
        1. 7.6.7.1 HS Gate Driver Control (address = 0x5)
        2. 7.6.7.2 LS Gate Driver Control (address = 0x6)
        3. 7.6.7.3 Gate Drive Control (address = 0x7)
        4. 7.6.7.4 IC Operation (address = 0x9)
        5. 7.6.7.5 Shunt Amplifier Control (address = 0xA)
        6. 7.6.7.6 Voltage Regulator Control (address = 0xB)
        7. 7.6.7.7 VDS Sense Control (address = 0xC)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Average Current
        2. 8.2.2.2 MOSFET Slew Rates
        3. 8.2.2.3 Overcurrent Protection
        4. 8.2.2.4 Current Sense Amplifiers
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

PHP Package
48-Pin HTQFP
Top View
DRV8305 po_lvscx2.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 EN_GATE I Enable gate Enables the gate driver and current shunt amplifiers; internal pulldown
2 INHA I Bridge PWM input PWM input signal for bridge A high-side
3 INLA I Bridge PWM input PWM input signal for bridge A low-side
4 INHB I Bridge PWM input PWM input signal for bridge B high-side
5 INLB I Bridge PWM input PWM input signal for bridge B low-side
6 INHC I Bridge PWM input PWM input signal for bridge C high-side
7 INLC I Bridge PWM input PWM input signal for bridge C low-side
8 nFAULT OD Fault indicator When low indicates a fault has occurred; open drain; external pullup to MCU power supply needed (1 kΩ to 10 kΩ)
9 nSCS I SPI chip select Select/enable for SPI; active low
10 SDI I SPI input SPI input signal
11 SDO O SPI output SPI output signal; referred to VREG
12 SCLK I SPI clock SPI clock signal
13 PWRGD OD Power Good VREG and MCU watchdog fault indication; open drain; external pullup to MCU power supply needed (1 kΩ to 10 kΩ)
14 GND P Device ground Must be connected to ground
45
PPAD
15 AVDD P Analog regulator 5.0 V analog internal supply regulator; bypass to GND with a 6.3-V, 1-µF ceramic capacitor
16 SO1 O Current amplifier output Output of current sense amplifier 1
17 SO2 O Current amplifier output Output of current sense amplifier 2
18 SO3 O Current amplifier output Output of current sense amplifier 3
19 SN3 I Current amplifier negative input Negative input of current sense amplifier 3
20 SP3 I Current amplifier positive input Positive input of current sense amplifier 3
21 SN2 I Current amplifier negative input Negative input of current sense amplifier 2
22 SP2 I Current amplifier positive input Positive input of current sense amplifier 2
23 SN1 I Current amplifier negative input Negative input of current sense amplifier 1
24 SP1 I Current amplifier positive input Positive input of current sense amplifier 1
25 GLC O Low-side gate driver Low-side gate driver output for half-bridge C
26 SLC I Low-side source connection Low-side source connection for half-bridge C
27 SHC I High-side source connection High-side source connection for half-bridge C
28 GHC O High-side gate driver High-side gate driver output for half-bridge C
29 GHB O High-side gate driver High-side gate driver output for half-bridge B
30 SHB I High-side source connection High-side source connection for half-bridge B
31 SLB I Low-side source connection Low-side source connection for half-bridge B
32 GLB O Low-side gate driver Low-side gate driver output for half-bridge B
33 GLA O Low-side gate driver Low-side gate driver output for half-bridge A
34 SLA I Low-side source connection Low-side source connection for half-bridge A
35 SHA I High-side source connection High-side source connection for half-bridge A
36 GHA O High-side gate driver High-side gate driver output for half-bridge A
37 VCP_LSD P Low-side gate driver regulator Internal voltage regulator for low-side gate driver; connect 1-µF capacitor to GND
38 VCPH P High-side gate driver regulator Internal voltage regulator for high-side gate driver; connect 2.2-µF capacitor to PVDD
39 CP2H P Charge pump flying capacitor Flying capacitor for charge pump; connect 0.047-µF capacitor between CP2H and CP2L
40 CP2L P

External Components

COMPONENT PIN 1 PIN 2 RECOMMENDED
CPVDD PVDD GND 4.7-µF ceramic capacitor rated for 50 V
CAVDD AVDD GND 1.0-µF ceramic capacitor rated for 6.3 V
CDVDD DVDD GND 1.0-µF ceramic capacitor rated for 6.3 V
CVCPH VCPH PVDD 2.2-µF ceramic capacitor rated for 16 V
CVCP_LSD VCP_LSD GND 1.0-µF ceramic capacitor rated for 16 V
CCP1 CP1H CP1L 0.047-µF ceramic capacitor rated for 16 V
CCP2 CP2H CP2L 0.047-µF ceramic capacitor rated for 16 V
CVREG VREG GND 1.0-µF ceramic capacitor rated for 6.3 V
RVDRAIN VDRAIN PVDD 100-Ω series resistor
RnFAULT nFAULT VCC (1) 1 to 10 kΩ pulled up the MCU power supply
(1) VCC is not a pin on the DRV8305, but a VCC supply voltage pullup is required for open-drain output nFAULT
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