Table 3. 1-PWM Active Freewheeling

Table 4. 1-PWM Diode Freewheeling

7.3.10.1 Fault and Protection Handling

The DRV8305 handles fault (latched fault) and warnings (unlatched faults) separately. Both latched and unlatched faults are reported in status registers and can be read through SPI.

• A latched nFAULT pin indicates an error event has occurred that has caused part of the gate driver to shut down and force outputs to a safe state (external FETs in high impedance).
  • A latched fault is indicated by the nFAULT pin going low (and staying low) and reporting the details of the fault in the status registers (0x02 and 0x03). The appropriate recovery sequence must be performed in order to reset the latched fault. In addition, the register (0x01) contains a single status bit if any latched faults are detected.
  • The nFAULT pin will stay low until the appropriate recovery sequence is performed.

TI recommends to inspect the system and board when a latched nFAULT faults occurs.

• An unlatched warning on nFAULT pin indicates that an event that requires a warning to be communicated has occurred.
  • An unlatched fault is indicated by the nFAULT pin going low for a period of 64 µs, reporting the warning and then recovering back high for a period of 64 µs before reporting any subsequent errors.
  • When a warning has been read by SPI through the warning register (0x01), that same warning will not be reported through nFAULT again unless that warning or condition passes and then reoccurs.

  However, the SPI registers will continue to report the latest status of the condition even after it has been cleared by the read, that is, if the condition has cleared, then the warning will clear in the SPI registers.

  Note that if the microprocessor does not read the warning, then the nFAULT pin will continue to toggle.

  • In case another warning or warnings are received during the 64-µs period but after the warning register has been read, then after the expiration of 64 µs, the nFAULT pin will go high for another 64 µs and then report those warning or warnings by going low for another 64 µs.
  • If a latched fault occurs during a period where nFAULT is low, then the nFAULT pin will stay low.

Note that nFAULT is an open-drain signal and must be pulled up through an external resistor.

7.3.10.2 Shoothrough Protection

DRV8305 integrates analog and digital monitors to prevent shoot-through in the external FETs.

• An Internal handshake through analog comparators is performed between high-side and low-side FETs during switching transition.
• A minimum dead time (digital) of 40 ns is always inserted after a successful handshake. This digital dead-time is programmable and is in addition to the time taken for the handshake.

7.3.10.3 VDS Sensing – External FET Protection and Reporting (OC Event)

To protect the external FETs from damage due to high currents, V_DS sensing circuitry is implemented in the DRV8305.

The V_DS sensing is implemented for both the high-side and low-side MOSFET through these pins:

• High-side MOSFET: V_DS measured between VDRAIN and SHX pins
• Low-side MOSFET: V_DS measured between SHX and SLX pins

Based on R_DS(on) of the power MOSFETs and the maximum allowed I_DS, a voltage threshold can be calculated, which when exceeded, triggers the V_DS protection feature.

This voltage threshold level is programmable through SPI command and may be programmed during operation if needed.

The V_DS protection logic also has an adjustable blanking time and deglitch time to prevent false trips.

V_DS blanking time (t_BLANK): This time is inserted digitally and is programmable. The t_BLANK time is a delay inserted at each output after that particular output has been commanded to turn ON. During t_BLANK time, the VDS comparators are not being monitored in order to prevent false trips when the FETs first turn ON.

V_DS deglitch time (t_VDS): This time is inserted digitally and is programmable. The t_VDS time is a delay inserted after the VDS sensing comparators have tripped to when the protection logic is informed that a VDS event has occurred.

Note that the dead time and blanking time are overlapping counters as shown in Figure 9

Figure 9. VDS Protection Timing

Three overcurrent responses are possible depending on the configuration option selected through SPI.

• V_DS event latch shutdown mode

When a VDS event occurs, device will pull all outputs low in order to take all six external FETs into high-impedance mode. The Fault will be reported on nFAULT and details of the FET that reported the fault can be read back through SPI.

• V_DS event Reporting only mode

In this mode, VDS event will be reported on the nFAULT pin and the SPI register. Gate drivers will continue to operate.

• V_DS event disable mode

Device ignores all the V_DS event detections and does not report them.

7.3.10.4 Low-Side Source Monitoring (SNS_OCP)

The DRV8305 monitors the voltage on the SLX pins for high-current events like phase shorts that may cause the voltage on those pins to exceed 2 V. The device will put the FETs into a high-impedance state to avoid damage.

7.3.11.1 Battery Overvoltage Protection (PVDD_OV)

The DRV8305 implements appropriate overvoltage responses in order to protect the system.

PVDD is monitored for overvoltage conditions. If the overvoltage threshold is tripped, a warning is issued and the event is reported in the status registers. The device takes no action.

7.3.11.2 Charge Pump Overvoltage Protection (VCPH_OV/VCP_LSD_OV)

If VCPH or VCP_LSD exceed the overvoltage threshold due to potential issue related to the charge pumps (for example, short of external charge pump capacitor or charge pump, an overvoltage fault is triggered).

7.3.11.3 Overtemperature (OT) Warning and Protection

A multi-level temperature detection circuit is implemented:

• Flag Level 1: Level 1 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set to indicate flag and can be read through SPI.
• Flag Level 2: Level 2 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set to indicate flag and can be read through SPI.
• Flag Level 3: Level 3 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set to indicate flag and can be read through SPI.
• Flag Level 4: Level 4 overtemperature flag. No warning is reported on nFAULT. A real-time register bit is set to indicate flag and can be read through SPI.
• Warning Level: Overtemperature warning only. Warning is reported on nFAULT for 64 µs and can be read through SPI.
• Fault Level: Overtemperature fault and latched shut down of gate driver and charge pump Fault will be reported to nFAULT pin.

SPI operation is still available and register settings will be retained in the device during OTSD operation as long as PVDD is still within defined operation range.

The details of the fault will be reported into a register that can be read back through SPI.

7.3.11.4 dV/dt Protection

The DRV8305 gate driver implements a strong pulldown scheme for preventing dV/dt turn on of external FETs. After a FET has been turned off using the selected sink slew rate setting, the internal state machine will turn on a stronger pulldown if it senses that the opposite FET on that phase has been commanded to turn on. This allows the systems designer to decouple the optimum slew rate setting selection for EMI and power from the pull down required to prevent dV/dt turn on.

7.3.11.5 VGS Protection

The DRV8305 gate driver uses a multilevel level protection scheme to protect the external FET from VGS voltages that may damage the gate of the external FET.

The device integrates VGS clamps inside the gate driver that will turn on when the GHX voltage exceeds SHX voltage by a value that could be damaging to the FETs. If the voltage continues to rise, in spite of the clamps turning on, the TDRIVE architecture ensures that the energy through the clamps is limited. If the high VGS voltage is due to an abnormal condition on the charge pump, the charge pump overvoltage fault will trip in order to protect the FETs from damage.

7.3.11.6 Gate Driver Faults

The DRV8305 protects against abnormal short to battery or short to ground conditions on the gate driver outputs that could result in an incorrect state of the gate driver outputs. The gate driver integrates VGS comparators that check the status of the gate driver output against the commanded PWM signal to ensure that they match. This comparison occurs shortly after the expiration of the TDRIVE time. If the comparison indicates a mismatch, a gate driver fault is indicated.

7.3.11.7 Reverse Battery Protection

The VCPH pin on the DRV8305 is designed to be able to supply an external load of up to 10 mA. This feature allows implementation of an external reverse battery protection scheme using a MOS and a BJT. The MOS gate can be driven through VCP through a current limiting resistor to limit the current drawn from VCP. The current limit resistor must be sized not to exceed the maximum external load on VCPH.

The VDRAIN pin (sense) may also be protected against negative transients on it by use of a current limiting resistor. The current limit resistor must be sized not to exceed the maximum current load on the VDRAIN pin.

Figure 10. Typical Scheme for Reverse Battery Protection Using VCPH

7.3.11.8 MCU Watchdog

An MCU watchdog function may be enabled to ensure that the external controller that is instructing the DRV8305 is active and not in an unknown state.

SPI Watchdog must be enabled by writing a 1 to the WD_EN bit through SPI (default is disabled = 0).

When the SPI watchdog is enabled, an internal timer starts to countdown to an interval set by WD_dly bit.

To reset the watchdog, the address 0x01 (Status register) must be read by the microcontroller within the interval set by the register WD_dly.

If the timer is allowed to expire without the address 0x01 being read, the WD fault will get enabled.

Response to this fault is as follows:

• A Latched + PWRGD fault occurs on the DRV8305 and gate drivers are put into a safe state. The appropriate recovery sequence must be performed.
• PWRGD pin is taken low for 64 µs and then back high in order to reset the microcontroller.
• nFAULT is asserted
• WD_EN bit is cleared
• Report that the watchdog had expired through SPI bit WD_FAULT
• TI recommends that if the watchdog function is being used, the MCU software routine reads the status registers as part of its recovery or power-up routine in order to know whether a WD_FAULT had previously occurred.

Note that the fault results in clearing of the WD_EN bit and it will have to be set again to resume watchdog functionality.

7.3.12.1 EN_GATE

EN_GATE low is used to put the gate driver into standby mode. Note that EN_GATE has no effect on the LDO voltage regulator. When EN_GATE is low, the device will always put the MOSFET output stage to high impedance as long as PVDD is still present. EN_GATE is also used to reset the IC.

It is not possible to enter SLEEP mode without taking EN_GATE low and entering STANDBY mode first.

TI recommends to take EN_GATE for at least greater than 25 µs when it is asserted low to go into standby mode.

7.3.12.2 SPI Pins

SDO pin has to be tri-state, so a data bus line can be connected to multiple SPI slave devices. SCS pin is active low. When SCS is high, SDO is at high-impendence mode.

Ensure that SDO pin is always configured in the system as an output from DRV8305.

SDO pin must never be driven to ensure correct operation of DRV8305. SDO is referrenced to the VREG voltage.

7.3.13.1 Reg 09h CLR_FLTS

When CLR_FLTS bit is set to 1, all expired faults (latch/warn) will be cleared from the SPI status register. Also, the nFAULT pin will be released on the event of an expired Latched fault. CLR_FLTS provides a software reset option to DRV8305. The effect on nFAULT pin and SPI status registers is the same as pulling EN_GATE pin low and taking it HIGH.

CLR_FLTS bit self clears to 0 after SPI status register is reset and nFAULT pin is released.

7.4.1.1 POWER Up

During power-up, all internal circuits are enabled. The VREG will also be enabled based on the hardware configuration (see Voltage Regulator Control (address = 0xB) section). All gate drive outputs are held low and the nFAULT pin is taken low by the IC while power up is being executed.

7.4.1.2 STANDBY State

After the startup sequence is completed and the PVDD voltage is above V_{PVDD_UVLO2}, the DRV8305 will indicate successful and fault-free power up of all circuits by releasing the nFAULT pin.

The device will also enter STANDBY state any time that EN_GATE is taken low or a latched fault occurs.

Gate driver always has control of the power FETs even in STANDBY state.

TI recommends to set up the device control registers through SPI in the STANDBY state.

7.4.1.3 OPERATING State

Normal operation of the gate driver and current shunt amplifiers can be initiated by taking EN_GATE from a low state to a high state. In this state the charge pump is powered up and the driver is ready for operation.

7.4.1.4 SLEEP State

The SLEEP state is invoked by issuing a SLEEP command through SPI. After the SLEEP command is received, the VREG and the gate driver safely power down internally after a programmable delay.

The DRV8305 can then only be enabled through the WAKE pin which is a high-voltage-tolerant input pin.

For the DRV8305 to be brought out of SLEEP, the WAKE pin must be at a voltage greater than 3 V. This allows the WAKE to be driven, for example, directly by the battery through a switch, through the inhibit pin (INH) on standard LIN interface or through standard digital logic. The WAKE pin will only react to a wake-up command if PVDD > V_{PVDD_UVLO2}.

After the DRV8305 is out of SLEEP mode, all activity on the WAKE pin is ignored.

SLEEP state erases the values in the SPI control registers. TI does not recommend to write through SPI in SLEEP state.

7.5.1.1 SPI

SPI is used to set device configuration, operating parameters, and read out diagnostic information. The DRV8305 SPI operates in slave mode.

The SPI input data (SDI) word consists of a 16-bit word with 11-bit data and 5-bit (MSB) command. The SPI output data (SDO) word consists of 11-bit register data. (The first 5 bits (MSB) are to be ignored.)

A valid frame must meet following conditions:

• Clock must be low when nSCS goes low.
• It should have 16 full clock cycles.
• Clock must be low when nSCS goes high.

Data is always shifted out on the rising edge of the clock in the same frame following the 5-bit MSB.

Data is always sampled on the falling edge of the clock in the same frame following the 5-bit MSB.

When SCS is asserted high, any signals at the SCLK and SDI pins are ignored, and SDO is forced into a high-impedance state. When SCS transitions from HIGH to LOW, SDO is enabled and the SPI response word loads into the shift register based on 5-bit command.

The SCLK pin must be low when SCS transitions low. While SCS is low, at each rising edge of the clock, the response bit is serially shifted out on the SDO pin with MSB shifted out first.

While SCS is low, at each falling edge of the clock, the new control bit is sampled on the SDI pin. The SPI command bits are decoded to determine the register address and access type (read or write). The MSB will be shifted in first. If the word sent to SDI is less than 16 bits or more than 16 bits, it is considered a frame error and the data will not be written into the destination address. If it is a write command, the data will be ignored.

For a write command, the existing data in the register being written to is shifted out on SDO following the 5-bit MSB.

SCS should be taken high for at least 500 ns between frames.

7.5.1.2 SPI Format

SPI input data control word is 16-bit long, consisting of:

• 1 read or write bit W [15]
• 4 address bits A [14:11]
• 11 data bits D [10:0]

SPI output data response word is 11-bit long (first 5 bits are ignored) and its content is the content of the register being accessed

For a Write transaction: The response word is the data currently in the register being written to.

For a Read Command: The response word is the data currently in the register being read.

Table 10. Warning and Watchdog Reset Register Description

Table 11. OV/VDS Faults Register Description

Table 12. IC Faults Register Description

Table 13. Gate Driver VGS Faults Register Description

7.6.7.1 HS Gate Driver Control (address = 0x5)

7.6.7.2 LS Gate Driver Control (address = 0x6)

7.6.7.3 Gate Drive Control (address = 0x7)

7.6.7.4 IC Operation (address = 0x9)

7.6.7.5 Shunt Amplifier Control (address = 0xA)

7.6.7.6 Voltage Regulator Control (address = 0xB)

7.6.7.7 VDS Sense Control (address = 0xC)