7.3.6 Pin Diagrams

Figure 22 shows the input structure for the logic-level pins, PWM, DIR and nBRAKE. The input can be driven with a voltage or external resistor.

Figure 22. Logic-Level Input Pin Structure (PWM, DIR, and nBRAKE)

Figure 23 shows the input structure for the logic-level pin, ENABLE pin. The input can be driven with a voltage or external resistor. The VEXT represents the external voltage.

Figure 23. Logic-Level Input Pin Structure (ENABLE)

Figure 24 shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external pullup resistor to function properly.

Figure 24. Open-Drain Output Pin Structure

Figure 25 shows the structure of the seven level input pins, IDRIVE and VDS. The input can be set with an external resistor.

Figure 25. Seven Level Input Pin Structure