ZHCSHZ0A April   2018  – July 2018 DRV8306

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three Phase Smart Gate Drivers
        1. 7.3.1.1 PWM Control Mode (1x PWM Mode)
        2. 7.3.1.2 Hardware Interface Mode
        3. 7.3.1.3 Gate Driver Voltage Supplies
        4. 7.3.1.4 Smart Gate Drive Architecture
          1. 7.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 7.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 7.3.1.4.3 Gate Drive Clamp
          4. 7.3.1.4.4 Propagation Delay
          5. 7.3.1.4.5 MOSFET VDS Monitors
          6. 7.3.1.4.6 VDRAIN Sense Pin
      2. 7.3.2 DVDD Linear Voltage Regulator
      3. 7.3.3 Pulse-by-Pulse Current Limit
      4. 7.3.4 Hall Comparators
      5. 7.3.5 FGOUT Signal
      6. 7.3.6 Pin Diagrams
      7. 7.3.7 Gate-Driver Protective Circuits
        1. 7.3.7.1 VM Supply Undervoltage Lockout (UVLO)
        2. 7.3.7.2 VCP Charge-Pump Undervoltage Lockout (CPUV)
        3. 7.3.7.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
        4. 7.3.7.4 VSENSE Overcurrent Protection (SEN_OCP)
        5. 7.3.7.5 Gate Driver Fault (GDF)
        6. 7.3.7.6 Thermal Shutdown (OTSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gate Driver Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (ENABLE Reset Pulse)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Hall Sensor Configuration and Connection
        1. 8.1.1.1 Typical Configuration
        2. 8.1.1.2 Open Drain Configuration
        3. 8.1.1.3 Series Configuration
        4. 8.1.1.4 Parallel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Primary Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External MOSFET Support
            1. 8.2.1.2.1.1 Example
          2. 8.2.1.2.2 IDRIVE Configuration
            1. 8.2.1.2.2.1 Example
          3. 8.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 8.2.1.2.3.1 Example
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

RSM Package
32-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 25 PWR Device analog ground. Connect to system ground.
CPH 1 PWR Charge-pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
CPL 32 PWR Charge-pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
DIR 29 I Direction pin for setting the direction of the motor rotation to clockwise or counterclockwise. Internal pulldown resistor.
DVDD 26 PWR 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally.
ENABLE 24 I Gate driver enable. When this pin is logic low the device enters a low-power sleep mode. A 15 to 40-µs low pulse can be used to reset fault conditions.
FGOUT 28 OD Outputs a commutation zero crossing signal generated from Hall sensors.
GHA 5 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 11 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 12 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 7 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 9 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 14 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
HNA 20 I Hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs.
HNB 18 I Hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs.
HNC 16 I Hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs.
HPA 19 I Hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs.
HPB 17 I Hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs.
HPC 15 I Hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative Hall inputs.
IDRIVE 22 I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
ISEN 8 I Current sense for pulse-by-pulse current limit. Connect to low-side current sense resistor.
PGND 31 PWR Device power ground. Connect to system ground.
PWM 27 I PWM input for motor control. Set the output voltage and switching frequency of the phase voltage of the motor.
SHA 6 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 10 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 13 I High-side source sense input. Connect to the high-side power MOSFET source.
VCP 2 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
VDRAIN 4 I High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS 23 I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VM 3 PWR Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and PGND pins.
nBRAKE 30 I Causes motor to brake. Internal pulldown resistor.
nFAULT 21 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
(1) PWR = power, I = input, O = output, OD = open-drain
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