8.1.1 Internal Speed Control Loop Constraints

The DRV8308 device is a versatile speed controller and driver for small, 3-phase brushless motors. However, there are some limitations to its application.

The built-in speed control loop is designed to work optimally with motor electrical speeds from about 50 Hz up to 6.7 kHz. For an 8-pole motor, this translates into about 500 RPM up to more than 100000 RPM. For motors with higher pole counts, these speeds scale down; for lower pole counts, they scale up.

Operation is possible at slower or faster speeds, but speed control becomes less effective, especially if using the Hall sensors for speed feedback (as opposed to the FG input).

Typically, the speed loop is optimized (by setting the filter coefficients and gains) at one desired motor speed. Operation is possible with one set of parameters over a limited speed range (for example, 1000 RPM to 2000 RPM), However, operation over a very wide speed range requires different parameters. The use of the auto gain and auto advance features can extend the dynamic range up to 4×.

When using the SPI interface to program the registers, the parameters can be updated at any time, even while the motor is running. In this manner, a wider range of speeds can be accommodated by the speed loop.

When not using the internal speed loop (when controlling the motor using PWM input or register speed control), the limits imposed by the speed loop do not apply. An external speed control implementation (using a microcontroller, FPGA, or other logic) can essentially control the motor current directly.

However, if using sine commutation, there are limits to the minimum and maximum speed, which are dictated by the timers that are used to generate the commutation sequence. The commutation timer is a 25-bit timer clocked at 50 MHz; therefore, the longest time it can capture is 655 ms. This limits the slowest speed to about 1.5 Hz (or 23 RPM for an 8-pole motor). At the other extreme, there are 960 steps in each sine commutation cycle. To ensure that there is enough time for the steps, the maximum speed is that which generates 960 counts at 50 MHz, or 52 kHz. This corresponds to a maximum speed of 800000 RPM for an 8-pole motor.

When not using the internal speed loop and using 120° commutation (using all three Hall sensors), there are no speed limitations. Commutation is performed with combinational logic.

8.1.2 Hall Sensor Configurations and Connections

The Hall sensor inputs on the DRV8308 device are capable of interfacing with a variety of Hall sensors. Typically, a Hall element is used, which outputs a differential signal on the order of 100 mV. To use this type of sensor, the VREG5 regulator can be used to power the Hall sensor. Connections are as shown in Figure 25:

Figure 25. Hall Sensor Connections

Since the amplitude of the Hall sensor output signal is very low, often capacitors are placed across the Hall inputs to help reject noise coupled from the motor PWM. Typically capacitors from 1 to 100 nF are used.

Some motors use digital Hall sensors with open-drain outputs. These sensors can also be used with the DRV8308 device, with the addition of a few resistors:

Figure 26. Hall Resistors

The negative (xHN) inputs are biased to 2.5 V by a pair of resistors between VREG and ground. For open-collector Hall sensors, an additional pullup resistor to VREG is needed on the positive (xHP) input. Again, the VREG output can usually be used to supply power to the Hall sensors.

8.1.3 FG Amplifier Configurations and Connections

To improve speed control by providing a higher bandwidth speed feedback, often a magnetic pickup coil, commonly referred to as an FG generator, is used. This is typically implemented as a serpentine PCB trace on the motor PCB. This generates a low-level sine wave signal whose amplitude and frequency is proportional to the speed of the motor.

Since the FG trace is in close proximity to the motor coils, it is very susceptible to noise coupling from the PWM of the motor. Noise coupling into the FG circuit causes poor speed regulation, especially at low motor speeds. Startup is a particularly difficult situation, as the motor current is at a maximum, and the FG signal amplitude is low (in fact, 0 at the moment of startup). If noise couples into FG during startup, the speed loop interprets the noise as fast motor rotation, and lowers the PWM duty cycle. The result is slow startup of the motor. If this problem is suspected, looking at the FGOUT signal with an oscilloscope during startup should reveal it.

To address this, in addition to the resistors that set the gain of the FG amplifier (R1 and R2 in Figure 27), usually passive filter components are needed on the FG amplifier circuit.

Figure 27. FG Amplifier Circuit

Ideally, the user desires a large amount of rejection of the PWM frequency. However, the user needs to pass the frequency that corresponds to their fastest motor speed. As an example, a motor may put out 36 FG pulses per revolution. At 5000 RPM, this is a 3-kHz signal. If you operate the PWM at 25 kHz, you can set a single pole at 3 kHz and have significant rejection of the PWM frequency, and the higher harmonics of the PWM (which are typically more easily coupled) are rejected even more.

Because the amplitude of the FG signal also increases with higher motor speed, it is possible to set this pole at a much lower frequency than the maximum speed dictates. The optimal values need to be determined by testing on the actual motor.

This pole is set by C3 in Figure 27.

In addition to rejection of high frequency, the FG winding should be AC-coupled to the amplifier to prevent any issues with DC offsets. This capacitor (C1) must be large enough to allow the motor to start-up reliably, since the FG frequency and amplitude are very low at startup. Typically capacitors on the order of 100 nF to 1 µF are used here. The voltage is low, so a 6.3-V ceramic capacitor can be used.

Occasionally an additional small capacitor is used across the FG trace. This capacitor (C2 above) may not be needed, but it can help reject very high-frequency harmonics of the PWM (glitches). Capacitors between 330 and 2200 pF are typically used.

8.2.1 Design Requirements

This section describes design considerations.

8.2.2 Detailed Design Procedure

8.2.2.3 Speed Command Method

The DRV8308 can drive BLDCs using an open-loop 0% to 100% command, or using closed-loop speed control. When using closed-loop, the correct reference clock frequency (on CLKIN) must be calculated.

If DRV8308 register FGSEL is set to 00b to use Hall U to sense motor speed,

Equation 5.

N_POLES is the number of permanent magnet poles.

If DRV8308 register FGSEL is set to 10b to use FG to sense motor speed,

Equation 6.

N_FG is the number of FG cycles per motor revolution.

8.2.3 Application Curves

Figure 29. Closed-loop Efficiency vs Torque

Figure 31. Open-loop Efficiency vs Torque

Figure 33. Open-loop RPM vs Voltage

Figure 35. Phase Current with Sine Mode

Figure 37. V_gs with I_DRIVE = 10mA

Figure 30. Closed-loop RPM and Current vs Torque

Figure 32. Open-loop RPM and Current vs Torque

Figure 34. Phase Current with 120 Degrees Mode

Figure 36. Startup

Figure 38. V_gs with I_DRIVE = 20mA

8.3.1 RESET and ENABLE Considerations

Since the ENABLE function doubles as a sleep (low-power shutdown) function, there are some important considerations when asserting and deasserting ENABLE and RESET.

While the motor driver is enabled, the deassertion of ENABLE initiates a stop-and-power-down sequence. This sequence starts by disabling the motor (either braking or coasting depending on the BRKMOD bit), and waiting for rotation to stop. After rotation is stopped for 1 s (as determined by the absence of transitions on FGOUT), the internal circuitry is powered-down, the V5 regulator and power switch are disabled, and internal clocks are stopped.

In this low-power sleep state, the serial interface may still be used to read or write registers. All other logic is disabled.

After this stop-and-power-down sequence has been initiated (by deasserting the ENABLE pin for at least 1.2 µs, or by changing the state of the ENPOL bit), the sequence continues to completion, regardless of the state of ENABLE. If ENABLE is immediately returned to the active state, the motor slows and stops for 1 s, at which point it starts again.

If RESET is asserted during power-down (at any time after the deassertion of ENABLE is recognized), it is acted upon when ENABLE is again asserted, and the part powers-up.

If RESET is asserted when ENABLE is active, the motor is stopped similar to the sequence when ENABLE is deasserted. After it is stopped for 1 s, all internal registers are reloaded with the value contained in OTP memory, faults are cleared, and internal states (that is, the speed loop datapath) are initialized. The motor remains disabled until RESET is deasserted.

RESET and ENABLE may be connected together (if the ENPOL bit in OTP memory is programmed so that ENABLE is active low). When both signals are low, the motor is enabled; when both signals are high, the motor is disabled. As soon as the signals are returned to high, all registers are reloaded from OTP memory, faults are cleared, and the motor starts.