No protective action occurs after a OCP event in this mode. The overcurrent event is reported by driving the nFAULT pin low and setting the FAULT, OCP, and corresponding FET's OCP bits high in the SPI registers. DRV8311 continue to operate as usual. The external controller manages the overcurrent condition by acting appropriately. The reporting clears (nFAULT pin is released, FAULT, OCP, and corresponding FET's OCP bits are cleared) when the OCP condition clears and a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (t_RST).