ZHCSOY8B September 2021 – February 2022 DRV8311
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Output Stage
- 8.3.2 Control Modes
- 8.3.3 Device Interface Modes
- 8.3.4 AVDD Linear Voltage Regulator
- 8.3.5 Charge Pump
- 8.3.6 Slew Rate Control
- 8.3.7 Cross Conduction (Dead Time)
- 8.3.8 Propagation Delay
- 8.3.9 Pin Diagrams
- 8.3.10 Current Sense Amplifiers
- 8.3.11 Protections
- 8.4 Device Functional Modes
- 8.5 SPI Communication
- 9 DRV8311 Registers
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
8.3.11.3.2 OCP Automatic Retry (OCP_MODE = 000b or 001b)
After a OCP event in this mode, all the FETs are disabled and the nFAULT pin is driven low. The FAULT, OCP, and corresponding FET's OCP bits are set high in the SPI registers. Normal operation starts again automatically (driver operation, the nFAULT pin is released and corresponding FET's OCP bits are cleared) after the tRETRY time elapses. The FAULT and OCP stays latched high until clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST).
tRETRY configuration
- Slow retry time SLOW_TRETRY can be used for tRETRY period by configuring OCP_MODE to 000b
- Fast retry time FAST_TRETRY can be used for tRETRY period by configuring OCP_MODE to 001b
Figure 8-33 Overcurrent Protection - Automatic Retry Mode