Three reset pins are provided for independent control of half-­bridges A, B, and C. When RESET_X is asserted low, two power-stage FETs in half-bridges X are forced into a high-impedance (Hi-Z) state.

A rising-edge transition on reset input allows the device to resume operation after a shut-down fault. That is, when half-bridge X has OC shutdown in CBC mode, a low to high transition of RESET_X pin will clear the fault and FAULT pin. When an OTSD or OC shutdown in Latching mode occurs, all three RESET_A, RESET_B, and RESET_C need to have a low to high transition to clear the fault and reset FAULT signal.