In the case of device latched faults, the DRV8316C-Q1 family of devices goes to a partial shutdown state to help protect the power MOSFETs and system.

When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT bit to 1b in the SPI variant or issuing a reset pulse to the nSLEEP pin on either variant. The nSLEEP reset pulse (t_RST) consists of a high-to-low-to-high transition on the nSLEEP pin. The low period of the sequence should fall within the t_RST time window or else the device will start the complete shutdown sequence (low power sleep mode). The reset pulse has no effect on any of the regulators, device settings, or other functional blocks.