If at any time input supply voltage on the VM pins rises higher lower than the V_OVP threshold voltage, all of the integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and OVP bits are also latched high in the registers on SPI devices. Normal operation starts again (driver operation and the nFAULT pin is released) when the OVP condition clears. The OVP bit stays set until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (t_RST). Setting the OVP_EN bit high on the SPI devices enables this protection feature. The OVP threshold is programmable on the SPI variant and can be set to 22-V or 34-V based on the OVP_SEL bit. In hardware variant, the OVP protection is always enabled and set to a 34-V threshold.

Figure 8-42 Over Voltage Protection