ZHCSP68C December 2021 – October 2022 DRV8328
PRODUCTION DATA
Overcurrent is also monitored by sensing the voltage drop across the external current sense resistor between the LSS and GND pins. If at any time the voltage on the LSS input exceeds the VSEN_OCP threshold for longer than the tDS_DEG deglitch time, a SEN_OCP event is recognized. Afer detecting the SEN_OCP overcurrent event, all of the gate driver outputs are driven low to disable the external MOSFETs and the nFAULT pin is driven low. The VSENSE threshold is fixed at 0.5 V and deglitch time is fixed to 3 µs. After the SEN_OCP condition is cleared, the fault state remains latched and can be cleared through an nSLEEP pin reset pulse (tRST). SEN_OCP can be disabled by connecting VDSLVL to GVDD through a 100 kΩ resistor.