ZHCSQQ0A June   2022  – October 2022 DRV8329

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specification
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings Comm
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information 1pkg
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three BLDC Gate Drivers
        1. 8.3.1.1 PWM Control Modes
          1. 8.3.1.1.1 6x PWM Mode
          2. 8.3.1.1.2 3x PWM Mode
        2. 8.3.1.2 Device Hardware Interface
        3. 8.3.1.3 Gate Drive Architecture
          1. 8.3.1.3.1 Propagation Delay
          2. 8.3.1.3.2 Deadtime and Cross-Conduction Prevention
      2. 8.3.2 AVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Low-Side Current Sense Amplifiers
        1. 8.3.4.1 Current Sense Operation
      5. 8.3.5 Gate Driver Shutdown Sequence (DRVOFF)
      6. 8.3.6 Gate Driver Protective Circuits
        1. 8.3.6.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 8.3.6.2 AVDD Power on Reset (AVDD_POR)
        3. 8.3.6.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 8.3.6.4 BST Undervoltage Lockout (BST_UV)
        5. 8.3.6.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 8.3.6.6 VSENSE Overcurrent Protection (SEN_OCP)
        7. 8.3.6.7 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (nSLEEP Reset Pulse)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Three Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1  Motor Voltage
          2. 9.2.1.1.2  Bootstrap Capacitor and GVDD Capacitor Selection
          3. 9.2.1.1.3  Gate Drive Current
          4. 9.2.1.1.4  Gate Resistor Selection
          5. 9.2.1.1.5  System Considerations in High Power Designs
            1. 9.2.1.1.5.1 Capacitor Voltage Ratings
            2. 9.2.1.1.5.2 External Power Stage Components
            3. 9.2.1.1.5.3 Parallel MOSFET Configuration
          6. 9.2.1.1.6  Dead Time Resistor Selection
          7. 9.2.1.1.7  VDSLVL Selection
          8. 9.2.1.1.8  AVDD Power Losses
          9. 9.2.1.1.9  Current Sensing and Output Filtering
          10. 9.2.1.1.10 Power Dissipation and Junction Temperature Losses
      2. 9.2.2 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3 Feature Description

Table 8-1 lists the recommended values of the external components for the gate driver and the buck regulator.

Table 8-1 DRV8329 External Components
COMPONENTS PIN 1 PIN 2 RECOMMENDED
CPVDD1 PVDD PGND X5R or X7R, 0.1-µF, >2x PVDD-rated capacitor
CPVDD2 PVDD PGND ≥ 10 µF, >2x PVDD-rated capacitor
CCP CPH CPL X5R or X7R, 470-nF, PVDD-rated capacitor
CGVDD GVDD GND X5R or X7R, ≥10-uF, 25V-rated capacitor
CAVDD AVDD AGND X5R or X7R, ≥1-µF, 6.3-V capacitor
CBSTx BSTx SHx X5R or X7R, 1-µF (typical), 25V-rated capacitor
RnFAULT VCC(1) nFAULT Pullup resistor (10 kΩ)
RDT DT AGND Hardware interface resistor. Refer to Section 8.3.1.3.2 for the details.
(1) The VCC pin is not a pin on the DRV8329 , but a VCC supply voltage pullup is required for the open-drain output, nFAULT. This pin can also be pulled up to AVDD.
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