The device integrates a programmable window-type SPI watchdog timer to verify that the external controller is operating. The SPI watchdog timer can be enabled by writing a 1 to WDT_EN SPI register bit. The watchdog timer is disabled by default. When the watchdog timer is enabled, an internal timer starts to count up. A valid SPI access resets the timer. This valid SPI access must be issued between the lower window time and the upper window time. If a watchdog timer fault is detected, nFAULT pin is asserted low.