ZHCSIN3A August   2018  – June  2019 DRV8350 , DRV8350R , DRV8353 , DRV8353R

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions—32-Pin DRV8350 Devices
    2.     Pin Functions—48-Pin DRV8350R Devices
    3.     Pin Functions—40-Pin DRV8353 Devices
    4.     Pin Functions—48-Pin DRV8353R Devices
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three Phase Smart Gate Drivers
        1. 8.3.1.1 PWM Control Modes
          1. 8.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
          2. 8.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
          3. 8.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
          4. 8.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
        2. 8.3.1.2 Device Interface Modes
          1. 8.3.1.2.1 Serial Peripheral Interface (SPI)
          2. 8.3.1.2.2 Hardware Interface
        3. 8.3.1.3 Gate Driver Voltage Supplies and Input Supply Configurations
        4. 8.3.1.4 Smart Gate Drive Architecture
          1. 8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 8.3.1.4.3 Propagation Delay
          4. 8.3.1.4.4 MOSFET VDS Monitors
          5. 8.3.1.4.5 VDRAIN Sense and Reference Pin
      2. 8.3.2 DVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Low-Side Current-Shunt Amplifiers (DRV8353 and DRV8353R Only)
        1. 8.3.4.1 Bidirectional Current Sense Operation
        2. 8.3.4.2 Unidirectional Current Sense Operation (SPI only)
        3. 8.3.4.3 Amplifier Calibration Modes
        4. 8.3.4.4 MOSFET VDS Sense Mode (SPI Only)
      5. 8.3.5 Step-Down Buck Regulator
        1. 8.3.5.1 Functional Block Diagram
        2. 8.3.5.2 Feature Description
          1. 8.3.5.2.1 Control Circuit Overview
          2. 8.3.5.2.2 Start-Up Regulator (VCC)
          3. 8.3.5.2.3 Regulation Comparator
          4. 8.3.5.2.4 Overvoltage Comparator
          5. 8.3.5.2.5 On-Time Generator and Shutdown
          6. 8.3.5.2.6 Current Limit
          7. 8.3.5.2.7 N-Channel Buck Switch and Driver
          8. 8.3.5.2.8 Thermal Protection
      6. 8.3.6 Gate Driver Protective Circuits
        1. 8.3.6.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
        2. 8.3.6.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
        3. 8.3.6.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
          1. 8.3.6.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.6.3.2 VDS Automatic Retry (OCP_MODE = 01b)
          3. 8.3.6.3.3 VDS Report Only (OCP_MODE = 10b)
          4. 8.3.6.3.4 VDS Disabled (OCP_MODE = 11b)
        4. 8.3.6.4 VSENSE Overcurrent Protection (SEN_OCP)
          1. 8.3.6.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.6.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
          3. 8.3.6.4.3 VSENSE Report Only (OCP_MODE = 10b)
          4. 8.3.6.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
        5. 8.3.6.5 Gate Driver Fault (GDF)
        6. 8.3.6.6 Overcurrent Soft Shutdown (OCP Soft)
        7. 8.3.6.7 Thermal Warning (OTW)
        8. 8.3.6.8 Thermal Shutdown (OTSD)
        9. 8.3.6.9 Fault Response Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
      2. 8.4.2 Buck Regulator Functional Modes
        1. 8.4.2.1 Shutdown Mode
        2. 8.4.2.2 Active Mode
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 SPI
          1. 8.5.1.1.1 SPI Format
    6. 8.6 Register Maps
      1. 8.6.1 Status Registers
        1. 8.6.1.1 Fault Status Register 1 (address = 0x00h)
          1. Table 11. Fault Status Register 1 Field Descriptions
        2. 8.6.1.2 Fault Status Register 2 (address = 0x01h)
          1. Table 12. Fault Status Register 2 Field Descriptions
      2. 8.6.2 Control Registers
        1. 8.6.2.1 Driver Control Register (address = 0x02h)
          1. Table 14. Driver Control Field Descriptions
        2. 8.6.2.2 Gate Drive HS Register (address = 0x03h)
          1. Table 15. Gate Drive HS Field Descriptions
        3. 8.6.2.3 Gate Drive LS Register (address = 0x04h)
          1. Table 16. Gate Drive LS Register Field Descriptions
        4. 8.6.2.4 OCP Control Register (address = 0x05h)
          1. Table 17. OCP Control Field Descriptions
        5. 8.6.2.5 CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
          1. Table 18. CSA Control Field Descriptions
        6. 8.6.2.6 Driver Configuration Register (DRV8353 and DRV8353R Only) (address = 0x07h)
          1. Table 19. Driver Configuration Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Primary Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 External MOSFET Support
            1. 9.2.1.2.1.1 MOSFET Example
          2. 9.2.1.2.2 IDRIVE Configuration
            1. 9.2.1.2.2.1 IDRIVE Example
          3. 9.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 9.2.1.2.3.1 VDS Overcurrent Example
          4. 9.2.1.2.4 Sense-Amplifier Bidirectional Configuration (DRV8353 and DRV8353R)
            1. 9.2.1.2.4.1 Sense-Amplifier Example
          5. 9.2.1.2.5 Single Supply Power Dissipation
          6. 9.2.1.2.6 Single Supply Power Dissipation Example
          7. 9.2.1.2.7 Buck Regulator Configuration (DRV8350R and DRV8353R)
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Alternative Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Sense Amplifier Unidirectional Configuration
            1. 9.2.2.2.1.1 Sense-Amplifier Example
            2. 9.2.2.2.1.2 Dual Supply Power Dissipation
            3. 9.2.2.2.1.3 Dual Supply Power Dissipation Example
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Buck-Regulator Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 相关链接
    4. 12.4 接收文档更新通知
    5. 12.5 社区资源
    6. 12.6 商标
    7. 12.7 静电放电警告
    8. 12.8 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (DVDD, VCP, VGLS, VM)
IVM VM operating supply current VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V 8.5 13 mA
IVDRAIN VDRAIN operating supply current VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V 1.9 4 mA
ISLEEP Sleep mode supply current ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C 20 40 µA
ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C 100
tRST Reset pulse time ENABLE = 0 V period to reset faults 5 40 µs
tWAKE Turnon time VVM > VUVLO, ENABLE = 3.3 V to outputs ready 1 ms
tSLEEP Turnoff time ENABLE = 0 V to device sleep mode 1 ms
VDVDD DVDD regulator voltage IDVDD = 0 to 10 mA 4.75 5 5.25 V
VVCP VCP operating voltage
with respect to VDRAIN		 VVM = 15 V, IVCP = 0 to 25 mA 9 10.5 12 V
VVM = 12 V, IVCP = 0 to 20 mA 7.5 10 11.5
VVM = 10 V, IVCP = 0 to 15 mA 6 8 9.5
VVM = 9 V, IVCP = 0 to 10 mA 5.5 7.5 8.5
VVGLS VGLS operating voltage
with respect to GND		 VVM = 15 V, IVGLS = 0 to 25 mA 13 14.5 16 V
VVM = 12 V, IVGLS = 0 to 20 mA 10 11.5 12.5
VVM = 10 V, IVGLS = 0 to 15 mA 8 9.5 10.5
VVM = 9 V, IVGLS = 0 to 10 mA 7 8.5 9.5
LOGIC-LEVEL INPUTS (ENABLE, INHx, INLx, nSCS, SCLK, SDI)
VIL Input logic low voltage 0 0.8 V
VIH Input logic high voltage 1.5 5.5 V
VHYS Input logic hysteresis 100 mV
IIL Input logic low current VVIN = 0 V –5 5 µA
IIH Input logic high current VVIN = 5 V 50 70 µA
RPD Pulldown resistance To GND 100 kΩ
tPD Propagation delay INHx/INLx transition to GHx/GLx transition 200 ns
FOUR-LEVEL H/W INPUTS (GAIN, MODE)
VI1 Input mode 1 voltage Tied to GND 0 V
VI2 Input mode 2 voltage 47 kΩ ± 5% to tied GND 1.9 V
VI3 Input mode 3 voltage Hi-Z 3.1 V
VI4 Input mode 4 voltage Tied to DVDD 5 V
RPU Pullup resistance Internal pullup to DVDD 50 kΩ
RPD Pulldown resistance Internal pulldown to GND 84 kΩ
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
VI1 Input mode 1 voltage Tied to GND 0 V
VI2 Input mode 2 voltage 18 kΩ ± 5% tied to GND 0.8 V
VI3 Input mode 3 voltage 75 kΩ ± 5% tied to GND 1.7 V
VI4 Input mode 4 voltage Hi-Z 2.5 V
VI5 Input mode 5 voltage 75 kΩ ± 5% tied to DVDD 3.3 V
VI6 Input mode 6 voltage 18 kΩ ± 5% tied to DVDD 4.2 V
VI7 Input mode 7 voltage Tied to DVDD 5 V
RPU Pullup resistance Internal pullup to DVDD 73 kΩ
RPD Pulldown resistance Internal pulldown to GND 73 kΩ
OPEN DRAIN OUTPUTS (nFAULT, SDO)
VOL Output logic low voltage IO = 5 mA 0.125 V
IOZ Output high impedance leakage VO = 5 V –2 2 µA
GATE DRIVERS (GHx, GLx)
VGSH High-side gate drive voltage
with respect to SHx		 VVM = 15 V, IVCP = 0 to 25 mA 9 10.5 12 V
VVM = 12 , IVCP = 0 to 20 mA 7.5 10 11.5
VVM = 10 V, IVCP = 0 to 15 mA 6 8 9.5
VVM = 9 V, IVCP = 0 to 10 mA 5.5 7.5 8.5
VGSL Low-side gate drive voltage
with respect to PGND		 VVM = 15 V, IVGLS = 0 to 25 mA 9.5 11 12.5 V
VVM = 12 V, IVGLS = 0 to 20 mA 9 10.5 12
VVM = 10 V, IVGLS = 0 to 15 mA 7.5 9 10.5
VVM = 9 V, IVGLS = 0 to 10 mA 6.5 8 9.5
tDEAD Gate drive
dead time		 SPI Device DEAD_TIME = 00b 50 ns
DEAD_TIME = 01b 100
DEAD_TIME = 10b 200
DEAD_TIME = 11b 400
H/W Device 100
tDRIVE Peak current
gate drive time		 SPI Device TDRIVE = 00b 500 ns
TDRIVE = 01b 1000
TDRIVE = 10b 2000
TDRIVE = 11b 4000
H/W Device 4000
IDRIVEP Peak source
gate current		 SPI Device IDRIVEP_HS or IDRIVEP_LS = 0000b 50 mA
IDRIVEP_HS or IDRIVEP_LS = 0001b 50
IDRIVEP_HS or IDRIVEP_LS = 0010b 100
IDRIVEP_HS or IDRIVEP_LS = 0011b 150
IDRIVEP_HS or IDRIVEP_LS = 0100b 300
IDRIVEP_HS or IDRIVEP_LS = 0101b 350
IDRIVEP_HS or IDRIVEP_LS = 0110b 400
IDRIVEP_HS or IDRIVEP_LS = 0111b 450
IDRIVEP_HS or IDRIVEP_LS = 1000b 550
IDRIVEP_HS or IDRIVEP_LS = 1001b 600
IDRIVEP_HS or IDRIVEP_LS = 1010b 650
IDRIVEP_HS or IDRIVEP_LS = 1011b 700
IDRIVEP_HS or IDRIVEP_LS = 1100b 850
IDRIVEP_HS or IDRIVEP_LS = 1101b 900
IDRIVEP_HS or IDRIVEP_LS = 1110b 950
IDRIVEP_HS or IDRIVEP_LS = 1111b 1000
H/W Device IDRIVE = Tied to GND 50
IDRIVE = 18 kΩ ± 5% tied to GND 100
IDRIVE = 75 kΩ ± 5% tied to GND 150
IDRIVE = Hi-Z 300
IDRIVE = 75 kΩ ± 5% tied to DVDD 450
IDRIVE = 18 kΩ ± 5% tied to DVDD 700
IDRIVE = Tied to DVDD 1000
IDRIVEN Peak sink
gate current		 SPI Device IDRIVEN_HS or IDRIVEN_LS = 0000b 100 mA
IDRIVEN_HS or IDRIVEN_LS = 0001b 100
IDRIVEN_HS or IDRIVEN_LS = 0010b 200
IDRIVEN_HS or IDRIVEN_LS = 0011b 300
IDRIVEN_HS or IDRIVEN_LS = 0100b 600
IDRIVEN_HS or IDRIVEN_LS = 0101b 700
IDRIVEN_HS or IDRIVEN_LS = 0110b 800
IDRIVEN_HS or IDRIVEN_LS = 0111b 900
IDRIVEN_HS or IDRIVEN_LS = 1000b 1100
IDRIVEN_HS or IDRIVEN_LS = 1001b 1200
IDRIVEN_HS or IDRIVEN_LS = 1010b 1300
IDRIVEN_HS or IDRIVEN_LS = 1011b 1400
IDRIVEN_HS or IDRIVEN_LS = 1100b 1700
IDRIVEN_HS or IDRIVEN_LS = 1101b 1800
IDRIVEN_HS or IDRIVEN_LS = 1110b 1900
IDRIVEN_HS or IDRIVEN_LS = 1111b 2000
H/W Device IDRIVE = Tied to GND 100
IDRIVE = 18 kΩ ± 5% tied to GND 200
IDRIVE = 75 kΩ ± 5% tied to GND 300
IDRIVE = Hi-Z 600
IDRIVE = 75 kΩ ± 5% tied to DVDD 900
IDRIVE = 18 kΩ ± 5% tied to DVDD 1400
IDRIVE = Tied to DVDD 2000
IHOLD Gate holding current Source current after tDRIVE 50 mA
Sink current after tDRIVE 100
ISTRONG Gate strong pulldown current GHx to SHx and GLx to SPx/SLx 2 A
ROFF Gate hold off resistor GHx to SHx and GLx to SPx/SLx 150 kΩ
CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)
GCSA Amplifier gain SPI Device CSA_GAIN = 00b 4.85 5 5.15 V/V
CSA_GAIN = 01b 9.7 10 10.3
CSA_GAIN = 10b 19.4 20 20.6
CSA_GAIN = 11b 38.8 40 41.2
H/W Device GAIN = Tied to GND 4.85 5 5.15
GAIN = 47 kΩ ± 5% tied to GND 9.7 10 10.3
GAIN = Hi-Z 19.4 20 20.6
GAIN = Tied to DVDD 38.8 40 41.2
tSET Settling time to ±1% VO_STEP = 0.5 V, GCSA = 5 V/V 250 ns
VO_STEP = 0.5 V, GCSA = 10 V/V 500
VO_STEP = 0.5 V, GVSA = 20 V/V 1000
VO_STEP = 0.5 V, GCSA = 40 V/V 2000
VCOM Common mode input range –0.15 0.15 V
VDIFF Differential mode input range –0.3 0.3 V
VOFF Input offset error VSP = VSN = 0 V –3 3 mV
VDRIFT Drift offset VSP = VSN = 0 V 10 µV/°C
VLINEAR SOx output voltage linear range 0.25 VVREF – 0.25 V
VBIAS SOx output voltage bias SPI Device VSP = VSN = 0 V, VREF_DIV = 0b VVREF – 0.3 V
VSP = VSN = 0 V, VREF_DIV = 1b VVREF / 2
H/W Device VSP = VSN = 0 V VVREF / 2
IBIAS SPx/SNx input bias current 250 µA
VSLEW SOx output slew rate 60-pF load 10 V/µs
IVREF VREF input current VVREF = 5 V 1.5 2.5 mA
UGB Unity gain bandwidth DRV835x: 60-pF load 10 MHz
DRV835xR: 60-pF load 1 MHz
PROTECTION CIRCUITS
VVM_UV VM undervoltage lockout DRV835x: VM falling, UVLO report 8.0 8.3 8.8 V
DRV835x: VM rising, UVLO recovery 8.2 8.5 9.0
DRV835xR: VM falling, UVLO report 8.0 8.3 8.6
DRV835xR: VM rising, UVLO recovery 8.2 8.5 8.8
VVM_UVH VM undervoltage hysteresis Rising to falling threshold 200 mV
tVM_UVD VM undervoltage deglitch time VM falling, UVLO report 10 µs
VVDR_UV VDRAIN undervoltage lockout DRV835x: VDRAIN falling, UVLO report 6.1 6.4 6.8 V
DRV835x: VDRAIN rising, UVLO recovery 6.3 6.6 7.0
DRV835xR: VDRAIN falling, UVLO report 6.1 6.4 6.7
DRV835xR: VDRAIN rising, UVLO recovery 6.3 6.6 6.9
VVDR_UVH VDRAIN undervoltage hysteresis Rising to falling threshold 200 mV
tVDR_UVD VDRAIN undervoltage deglitch time VDRAIN falling, UVLO report 10 µs
VVCP_UV VCP charge pump undervoltage lockout VCP falling, GDUV report VDRAIN + 5 V
VVGLS_UV VGLS low-side regulator undervoltage lockout VGLS falling, GDUV report 4.25 V
VGS_CLAMP High-side gate clamp Positive clamping voltage 12.5 13.5 16 V
Negative clamping voltage –0.7
VVDS_OCP VDS overcurrent
trip voltage		 SPI Device DRV835x: VDS_LVL = 0000b 0.041 0.06 0.072 V
DRV835x: VDS_LVL = 0001b 0.051 0.07 0.084
DRV835x: VDS_LVL = 0010b 0.061 0.08 0.096
DRV835x: VDS_LVL = 0011b 0.071 0.09 0.108
DRV835x: VDS_LVL = 0100b 0.081 0.1 0.115
DRV835xR: VDS_LVL = 0000b 0.048 0.06 0.072
DRV835xR: VDS_LVL = 0001b 0.056 0.07 0.084
DRV835xR: VDS_LVL = 0010b 0.064 0.08 0.096
DRV835xR: VDS_LVL = 0011b 0.072 0.09 0.108
DRV835xR: VDS_LVL = 0100b 0.085 0.1 0.115
VDS_LVL = 0101b 0.18 0.2 0.22
VDS_LVL = 0110b 0.27 0.3 0.33
VDS_LVL = 0111b 0.36 0.4 0.44
VDS_LVL = 1000b 0.45 0.5 0.55
VDS_LVL = 1001b 0.54 0.6 0.66
VDS_LVL = 1010b 0.63 0.7 0.77
VDS_LVL = 1011b 0.72 0.8 0.88
VDS_LVL = 1100b 0.81 0.9 0.99
VDS_LVL = 1101b 0.9 1.0 1.1
VDS_LVL = 1110b 1.35 1.5 1.65
VDS_LVL = 1111b 1.8 2 2.2
H/W Device DRV835x: VDS = Tied to GND 0.041 0.06 0.072 V
DRV835x: VDS = 18 kΩ ± 5% tied to GND 0.081 0.1 0.115
DRV835xR: VDS = Tied to GND 0.048 0.06 0.072
DRV835xR: VDS = 18 kΩ ± 5% tied to GND 0.085 0.1 0.115
VDS = 75 kΩ ± 5% tied to GND 0.18 0.2 0.22
VDS = Hi-Z 0.36 0.4 0.44
VDS = 75 kΩ ± 5% tied to DVDD 0.63 0.7 0.77
VDS = 18 kΩ ± 5% tied to DVDD 0.9 1 1.1
VDS = Tied to DVDD Disabled
tOCP_DEG VDS and VSENSE overcurrent deglitch time SPI Device OCP_DEG = 00b 1 µs
OCP_DEG = 01b 2
OCP_DEG = 10b 4
OCP_DEG = 11b 8
H/W Device 4
VSEN_OCP VSENSE overcurrent trip voltage SPI Device SEN_LVL = 00b 0.25 V
SEN_LVL = 01b 0.5
SEN_LVL = 10b 0.75
SEN_LVL = 11b 1
H/W Device 1
tRETRY Overcurrent retry time SPI Device TRETRY = 0b 8 ms
TRETRY = 1b 50 μs
H/W Device 8 ms
TOTW Thermal warning temperature Die temperature, TJ 130 150 170 °C
TOTSD Thermal shutdown temperature Die temperature, TJ 150 170 190 °C
THYS Thermal hysteresis Die temperature, TJ 20 °C
BUCK REGULATOR VCC
VVCC_REG VCC regulator voltage 6.6 7 7.4 V
VVIN = 6 to 8.5 V 100 mV
VVCC_BYT VCC bypass threshold VVIN increasing 8.5 V
VVCC_BYH VCC bypass hysteresis 300 mV
VVCC_OUT VCC output impedance VVIN = 6 V 100 Ω
VVIN = 10 V 8.8 Ω
VVIN = 48 V 0.8 Ω
VVCC_LIM VCC current limit 9.2 mA
VVCC_UV VCC undervoltage lockout 5.3 V
VVCC_UVH VCC undervoltage lockout hysteresis 190 mV
VVCC_UVFD VCC filter delay 3 μs
IIN_OP IIN operating current FB = 3 V 550 750 μA
IIN_OP IIN shutdown current RT/SD = 0 V 110 176 μA
BUCK REGULATOR SWITCHING
RDS(on) Buck switch RDS(on) ITEST = 200 mA 1.25 2.57 Ω
VGATE_UV Gate drive undervoltage lockout VBST - VSW rising 2.8 3.8 4.8 V
VGATE_UVH Gate drive undervoltage lockout hysteresis 490 mV
VSWITCH Pre-charge switch voltage At 1 mA 0.8 V
tON Pre-charge switch on-time 150 ns
BUCK REGULATOR CURRENT LIMIT
ILIMIT Current limit threshold 0.41 0.51 0.61 A
tLIM Current limit response time ISW overdrive = 0.1 A, time to switch off 350 ns
tOFF1 Off time generator FB = 0 V, RCL = 100 kΩ 35 μs
tOFF2 Off time generator FB = 2.3 V, RCL = 100 kΩ 2.56 μs
BUCK REGULATOR ON TIME GENERATOR
tON1 Ton 1 VVIN = 10 V, RON = 200 kΩ 2.15 2.77 3.5 μs
tON2 Ton 2 VVIN = 95 V, RON = 200 kΩ 200 300 420 μs
VSDT Remote shutdown threshold Rising 0.4 0.7 1.05 V
VSDH Remote shutdown hysteresis 35 mV
BUCK REGULATOR MINIMUM OFF TIME
tOFF_MIN Minimum off time FB = 0 V 300 ns
BUCK REGULATOR REGULATIONS AND OV COMPARATORS
VFB FB reference threshold Internal reference, trip point for switch on 2.445 2.5 2.55 V
VFB_OV FB overvoltage threshold Trip point for switch off 2.875 V
IFB_BIAS FB bias current 100 μA
BUCK REGULATOR THERMAL SHUTDOWN
TSD Thermal shutdown threshold 165 °C
TSDH Thermal shutdown hysteresis 25 °C
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