ZHCSR67 July 2020 DRV8353M
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Absolute Maximum Ratings
- 8 ESD Ratings
- 9 Recommended Operating Conditions
- 10Thermal Information
- 11Electrical Characteristics
- 12SPI Timing Requirements
-
13Detailed Description
- 13.1 Overview
- 13.2 Functional Block Diagram
- 13.3
Feature Description
- 13.3.1 Three Phase Smart Gate Drivers
- 13.3.2 DVDD Linear Voltage Regulator
- 13.3.3 Pin Diagrams
- 13.3.4 Low-Side Current-Shunt Amplifiers
- 13.3.5
Gate Driver Protective Circuits
- 13.3.5.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
- 13.3.5.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
- 13.3.5.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 13.3.5.4 VSENSE Overcurrent Protection (SEN_OCP)
- 13.3.5.5 Gate Driver Fault (GDF)
- 13.3.5.6 Overcurrent Soft Shutdown (OCP Soft)
- 13.3.5.7 Thermal Warning (OTW)
- 13.3.5.8 Thermal Shutdown (OTSD)
- 13.3.5.9 Fault Response Table
- 13.4 Device Functional Modes
- 13.5 Programming
- 13.6
Register Maps
- 13.6.1 Status Registers
- 13.6.2
Control Registers
- 13.6.2.1 Driver Control Register (address = 0x02h)
- 13.6.2.2 Gate Drive HS Register (address = 0x03h)
- 13.6.2.3 Gate Drive LS Register (address = 0x04h)
- 13.6.2.4 OCP Control Register (address = 0x05h)
- 13.6.2.5 CSA Control Register (address = 0x06h)
- 13.6.2.6 Driver Configuration Register (address = 0x07h)
-
14Application and Implementation
- 14.1 Application Information
- 14.2
Typical Application
- 14.2.1
Primary Application
- 14.2.1.1 Design Requirements
- 14.2.1.2 Detailed Design Procedure
- 14.2.1.3 Application Curves
- 14.2.1
Primary Application
- 15Power Supply Recommendations
- 16Layout
- 17Device and Documentation Support
- 18Mechanical, Packaging, and Orderable Information
13.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
In this mode, the corresponding input pin independently controls each high-side and low-side gate driver. This control mode allows for the external controller to bypass the internal dead-time handshake of the DRV8353M or to utilize the high-side and low-side drivers to drive separate high-side and low-side loads with each half-bridge. These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side switches. In this mode, If the system is configured in a half-bridge configuration, shoot-through occurs when the high-side and low-side MOSFETs are turned on at the same time.
| INLx | INHx | GLx | GHx |
|---|---|---|---|
| 0 | 0 | L | L |
| 0 | 1 | L | H |
| 1 | 0 | H | L |
| 1 | 1 | H | H |
Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using both of the monitors is not possible if both the high-side and low-side gate drivers are being operated independently.
In this case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in Figure 13-5.
Figure 13-5 Independent PWM High-Side and Low-Side DriversIf the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors is still possible. Connect the SHx pin as shown in Figure 13-6 or Figure 13-7. The unused gate driver and the corresponding input can be left disconnected.
Figure 13-6 Single High-Side Driver
Figure 13-7 Single Low-Side Driver