ZHCSR67 July 2020 DRV8353M
PRODUCTION DATA
In this mode, the DRV8353M family of devices uses 6-step block commutation tables that are stored internally. This feature allows for a three-phase BLDC motor to be controlled using a single PWM sourced from a simple controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the half-bridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic inputs. The state inputs can be controlled by an external controller or connected directly to hall sensor digital outputs from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode usually operates with synchronous rectification, however it can be configured to use asynchronous diode freewheeling rectification on SPI devices. This configuration is set using the 1PWM_COM bit through the SPI registers.
The INHC input controls the direction through the 6-step commutation table which is used to change the direction of the motor when hall sensors are directly controlling the INLA, INHB, and INLB state inputs. Tie the INHC pin low if this feature is not required.
The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs when it is pulled low. This brake is independent of the states of the other input pins. Tie the INLC pin high if this feature is not required.
LOGIC AND HALL INPUTS | GATE-DRIVE OUTPUTS | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STATE | INHC = 0 | INHC = 1 | PHASE A | PHASE B | PHASE C | DESCRIPTION | |||||||
INLA | INHB | INLB | INLA | INHB | INLB | GHA | GLA | GHB | GLB | GHC | GLC | ||
Stop | 0 | 0 | 0 | 0 | 0 | 0 | L | L | L | L | L | L | Stop |
Align | 1 | 1 | 1 | 1 | 1 | 1 | PWM | !PWM | L | H | L | H | Align |
1 | 1 | 1 | 0 | 0 | 0 | 1 | L | L | PWM | !PWM | L | H | B → C |
2 | 1 | 0 | 0 | 0 | 1 | 1 | PWM | !PWM | L | L | L | H | A → C |
3 | 1 | 0 | 1 | 0 | 1 | 0 | PWM | !PWM | L | H | L | L | A → B |
4 | 0 | 0 | 1 | 1 | 1 | 0 | L | L | L | H | PWM | !PWM | C → B |
5 | 0 | 1 | 1 | 1 | 0 | 0 | L | H | L | L | PWM | !PWM | C → A |
6 | 0 | 1 | 0 | 1 | 0 | 1 | L | H | PWM | !PWM | L | L | B → A |
LOGIC AND HALL INPUTS | GATE-DRIVE OUTPUTS | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STATE | INHC = 0 | INHC = 1 | PHASE A | PHASE B | PHASE C | DESCRIPTION | |||||||
INLA | INHB | INLB | INLA | INHB | INLB | GHA | GLA | GHB | GLB | GHC | GLC | ||
Stop | 0 | 0 | 0 | 0 | 0 | 0 | L | L | L | L | L | L | Stop |
Align | 1 | 1 | 1 | 1 | 1 | 1 | PWM | L | L | H | L | H | Align |
1 | 1 | 1 | 0 | 0 | 0 | 1 | L | L | PWM | L | L | H | B → C |
2 | 1 | 0 | 0 | 0 | 1 | 1 | PWM | L | L | L | L | H | A → C |
3 | 1 | 0 | 1 | 0 | 1 | 0 | PWM | L | L | H | L | L | A → B |
4 | 0 | 0 | 1 | 1 | 1 | 0 | L | L | L | H | PWM | L | C → B |
5 | 0 | 1 | 1 | 1 | 0 | 0 | L | H | L | L | PWM | L | C → A |
6 | 0 | 1 | 0 | 1 | 0 | 1 | L | H | PWM | L | L | L | B → A |
Figure 13-3 and Figure 13-4 show the different possible configurations in 1x PWM mode.