If at any time the voltage on the VCP pin (charge pump) falls below the V_{VCP_UV} threshold or voltage on the VGLS pin falls below the V_{VGLS_UV} threshold, all of the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT and GDUV bits are also latched high in the registers on SPI devices. Normal operation continues (gate-driver operation and the nFAULT pin is released) when the undervoltage condition is removed. The GDUV bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (t_RST). Setting the DIS_GDUV bit high on the SPI devices disables this protection feature. On hardware interface devices, the GDUV protection is always enabled.