ZHCSR67 July   2020 DRV8353M

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions—40-Pin DRV8353M Devices
  7. 7 Absolute Maximum Ratings
  8. 8 ESD Ratings
  9. 9 Recommended Operating Conditions
  10. 10Thermal Information
  11. 11Electrical Characteristics
  12. 12SPI Timing Requirements
  13. 13Detailed Description
    1. 13.1 Overview
    2. 13.2 Functional Block Diagram
    3. 13.3 Feature Description
      1. 13.3.1 Three Phase Smart Gate Drivers
        1. 13.3.1.1 PWM Control Modes
          1. 13.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
          2. 13.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
          3. 13.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
          4. 13.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
        2. 13.3.1.2 Device Interface Modes
          1. 13.3.1.2.1 Serial Peripheral Interface (SPI)
          2. 13.3.1.2.2 Hardware Interface
        3. 13.3.1.3 Gate Driver Voltage Supplies and Input Supply Configurations
        4. 13.3.1.4 Smart Gate Drive Architecture
          1. 13.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 13.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 13.3.1.4.3 Propagation Delay
          4. 13.3.1.4.4 MOSFET VDS Monitors
          5. 13.3.1.4.5 VDRAIN Sense and Reference Pin
      2. 13.3.2 DVDD Linear Voltage Regulator
      3. 13.3.3 Pin Diagrams
      4. 13.3.4 Low-Side Current-Shunt Amplifiers
        1. 13.3.4.1 Bidirectional Current Sense Operation
        2. 13.3.4.2 Unidirectional Current Sense Operation (SPI only)
        3. 13.3.4.3 Amplifier Calibration Modes
        4. 13.3.4.4 MOSFET VDS Sense Mode (SPI Only)
      5. 13.3.5 Gate Driver Protective Circuits
        1. 13.3.5.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
        2. 13.3.5.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
        3. 13.3.5.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
          1. 13.3.5.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
          2. 13.3.5.3.2 VDS Automatic Retry (OCP_MODE = 01b)
          3. 13.3.5.3.3 VDS Report Only (OCP_MODE = 10b)
          4. 13.3.5.3.4 VDS Disabled (OCP_MODE = 11b)
        4. 13.3.5.4 VSENSE Overcurrent Protection (SEN_OCP)
          1. 13.3.5.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
          2. 13.3.5.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
          3. 13.3.5.4.3 VSENSE Report Only (OCP_MODE = 10b)
          4. 13.3.5.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
        5. 13.3.5.5 Gate Driver Fault (GDF)
        6. 13.3.5.6 Overcurrent Soft Shutdown (OCP Soft)
        7. 13.3.5.7 Thermal Warning (OTW)
        8. 13.3.5.8 Thermal Shutdown (OTSD)
        9. 13.3.5.9 Fault Response Table
    4. 13.4 Device Functional Modes
      1. 13.4.1 Gate Driver Functional Modes
        1. 13.4.1.1 Sleep Mode
        2. 13.4.1.2 Operating Mode
        3. 13.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
    5. 13.5 Programming
      1. 13.5.1 SPI Communication
        1. 13.5.1.1 SPI
          1. 13.5.1.1.1 SPI Format
    6. 13.6 Register Maps
      1. 13.6.1 Status Registers
        1. 13.6.1.1 Fault Status Register 1 (address = 0x00h)
        2. 13.6.1.2 Fault Status Register 2 (address = 0x01h)
      2. 13.6.2 Control Registers
        1. 13.6.2.1 Driver Control Register (address = 0x02h)
        2. 13.6.2.2 Gate Drive HS Register (address = 0x03h)
        3. 13.6.2.3 Gate Drive LS Register (address = 0x04h)
        4. 13.6.2.4 OCP Control Register (address = 0x05h)
        5. 13.6.2.5 CSA Control Register (address = 0x06h)
        6. 13.6.2.6 Driver Configuration Register (address = 0x07h)
  14. 14Application and Implementation
    1. 14.1 Application Information
    2. 14.2 Typical Application
      1. 14.2.1 Primary Application
        1. 14.2.1.1 Design Requirements
        2. 14.2.1.2 Detailed Design Procedure
          1. 14.2.1.2.1 External MOSFET Support
            1. 14.2.1.2.1.1 MOSFET Example
          2. 14.2.1.2.2 IDRIVE Configuration
            1. 14.2.1.2.2.1 IDRIVE Example
          3. 14.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 14.2.1.2.3.1 VDS Overcurrent Example
          4. 14.2.1.2.4 Sense-Amplifier Bidirectional Configuration
            1. 14.2.1.2.4.1 Sense-Amplifier Example
          5. 14.2.1.2.5 Single Supply Power Dissipation
          6. 14.2.1.2.6 Single Supply Power Dissipation Example
        3. 14.2.1.3 Application Curves
  15. 15Power Supply Recommendations
    1. 15.1 Bulk Capacitance Sizing
  16. 16Layout
    1. 16.1 Layout Guidelines
    2. 16.2 Layout Example
  17. 17Device and Documentation Support
    1. 17.1 Device Support
      1. 17.1.1 Device Nomenclature
    2. 17.2 Documentation Support
      1. 17.2.1 Related Documentation
    3. 17.3 Receiving Notification of Documentation Updates
    4. 17.4 Support Resources
    5. 17.5 Trademarks
    6. 17.6 Electrostatic Discharge Caution
    7. 17.7 Glossary
  18. 18Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

Pin Functions—40-Pin DRV8353M Devices

DRV8353HM RTA Package 40-Pin VWQFN With Exposed Thermal PadTop View
DRV8353SM RTA Package 40-Pin VWQFN With Exposed Thermal PadTop View
PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8353HM DRV8353SM
AGND 25 25 PWR Device analog ground. Connect to system ground.
CPH 2 2 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
CPL 1 1 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins.
DVDD 38 38 PWR 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This regulator can source up to 10 mA externally.
ENABLE 31 31 I Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions.
GAIN 30 — I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GND 39 39 PWR Device power ground. Connect to system ground.
GHA 6 6 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 15 15 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 16 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 8 8 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 13 13 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 18 18 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE 28 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 32 32 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 34 34 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 36 36 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 33 33 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 35 35 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 37 37 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 27 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
nFAULT 26 26 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 30 I Serial chip select. A logic low on this pin enables serial interface communication.
SCLK — 29 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 28 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 27 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 7 7 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 14 14 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 17 17 I High-side source sense input. Connect to the high-side power MOSFET source.
SNA 10 10 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNB 11 11 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNC 20 20 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SOA 23 23 O Shunt amplifier output.
SOB 22 22 O Shunt amplifier output.
SOC 21 21 O Shunt amplifier output.
SPA 9 9 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPB 12 12 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPC 19 19 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
VCP 5 5 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN 4 4 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS 29 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS 40 40 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VM 3 3 PWR Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VREF 24 24 PWR Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
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