Figure 13-17 shows the input structure for the logic-level pins, INHx, INLx, ENABLE, nSCS, SCLK, and SDI.

Figure 13-17 Logic-Level Input Pin Structure

Figure 13-18 shows the structure of the four level input pins, MODE and GAIN, on hardware interface devices. The input can be set with an external resistor.

Figure 13-18 Four Level Input Pin Structure

Figure 13-19 shows the structure of the seven level input pins, IDRIVE and VDS, on hardware interface devices. The input can be set with an external resistor.

Figure 13-19 Seven Level Input Pin Structure

Figure 13-20 shows the structure of the open-drain output pins nFAULT and SDO. The open-drain output requires an external pullup resistor to function correctly.

Figure 13-20 Open-Drain Output Pin Structure