SLOSEC6 August   2024 DRV8434A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 STEP and DIR Timing Requirements
      1. 5.6.1 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Stepper Motor Driver Current Ratings
        1. 6.3.1.1 Peak Current Rating
        2. 6.3.1.2 RMS Current Rating
        3. 6.3.1.3 Full-Scale Current Rating
      2. 6.3.2 PWM Motor Drivers
      3. 6.3.3 Microstepping Indexer
      4. 6.3.4 Controlling VREF with an MCU DAC
      5. 6.3.5 Current Regulation and Decay Mode
        1. 6.3.5.1 Smart tune Ripple Control
        2. 6.3.5.2 Blanking time
      6. 6.3.6 Charge Pump
      7. 6.3.7 Linear Voltage Regulators
      8. 6.3.8 Logic Level, Tri-Level and Quad-Level Pin Diagrams
        1. 6.3.8.1 nFAULT and STL_REP Pin
      9. 6.3.9 Protection Circuits
        1. 6.3.9.1 VM Undervoltage Lockout (UVLO)
        2. 6.3.9.2 VCP Undervoltage Lockout (CPUV)
        3. 6.3.9.3 Overcurrent Protection (OCP)
        4. 6.3.9.4 Stall Detection
        5. 6.3.9.5 Open-Load Detection (OL)
        6. 6.3.9.6 Thermal Shutdown (OTSD)
        7.       Fault Condition Summary
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode (nSLEEP = 0)
      2.      43
      3. 6.4.2 Disable Mode (nSLEEP = 1, ENABLE = 0)
      4. 6.4.3 Operating Mode (nSLEEP = 1, ENABLE = Hi-Z/1)
      5. 6.4.4 nSLEEP Reset Pulse
      6.      Functional Modes Summary
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Stepper Motor Speed
        2. 7.2.2.2 Current Regulation
        3. 7.2.2.3 Decay Mode
        4. 7.2.2.4 Application Curves
        5. 7.2.2.5 Thermal Application
          1. 7.2.2.5.1 Power Dissipation
          2. 7.2.2.5.2 Conduction Loss
          3. 7.2.2.5.3 Switching Loss
          4. 7.2.2.5.4 Power Dissipation Due to Quiescent Current
          5. 7.2.2.5.5 Total Power Dissipation
          6. 7.2.2.5.6 Device Junction Temperature Estimation
  9. 8 Power Supply Recommendations
    1. 8.1 Bulk Capacitance
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

4.1 Pin Functions

PIN I/O TYPE DESCRIPTION
NAME

NO.
VQFN
AOUT1 3 O Output Winding A output. Connect to stepper motor winding.
AOUT2 4 O Output Winding A output. Connect to stepper motor winding.
PGND 2, 7 — Power Power ground. Connect to system ground.
BOUT2 5 O Output Winding B output. Connect to stepper motor winding
BOUT1 6 O Output Winding B output. Connect to stepper motor winding
CPH 23 — Power Charge pump switching node. Connect a X7R, 0.022-µF, VM-rated ceramic capacitor from CPH to CPL.
CPL 22
DIR 19 I Input Direction input. Logic level sets the direction of stepping; internal pulldown resistor.
ENABLE 20 I Input Logic low to disable device outputs; logic high to enable device outputs; Hi-Z to enable 8x torque count scaling.
DVDD 10 — Power Logic supply voltage. Connect a X7R, 0.47-μF to 1-μF, 6.3-V or 10-V rated ceramic capacitor to GND.
GND 9 — Power Device ground. Connect to system ground.
VREF 12 I Input Current set reference input. Maximum value 3.3 V. DVDD can be used to provide VREF through a resistor divider.
M0 13 I Input Microstepping mode-setting pins. Sets the step mode.
M1 17
STL_MODE 16 I Input

Pin input level programs the stall detection mode:

0 = Torque count mode, torque count analog voltage is output on the TRQ_CNT/STL_TH pin.

Hi-Z = Learning mode, learning result analog voltage is output on the TRQ_CNT/STL_TH pin.

1 = Stall threshold mode, stall threshold is set by an input voltage on the TRQ_CNT/STL_TH pin.

Tied to ground with a 330k resistor = Stall detection disabled.

TRQ_CNT/STL_TH 15 I/O Input/Output Torque count analog output or stall threshold analog input depending on STL_MODE pin input level. A 1nF capacitor must be connected from this pin to ground.
STEP 18 I Input Step input. A rising edge causes the indexer to advance one step; internal pulldown resistor.
VCP 24 — Power Charge pump output. Connect a X7R, 0.22-μF, 16-V ceramic capacitor to VM.
VM 1, 8 — Power Power supply. Connect to motor supply voltage and bypass to PGND with two 0.01-µF ceramic capacitors (one for each pin) plus a bulk capacitor rated for VM.
STL_REP 14 O Open Drain Stall fault report output. Requires a pullup resistor. A low to high transition indicates a stall. A high to low transition indicates a successful learning. If this pin is connected to ground, stall fault reporting is disabled.
nFAULT 11 O Open Drain Fault output. Pulled logic low when a fault is detected; open-drain output. Requires a pullup resistor.
nSLEEP 21 I Input Sleep mode control. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor. An nSLEEP low pulse clears faults.
PAD - - - Thermal pad. Connect to system ground.
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