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ZHCSG08E October 2016 – January 2021 DRV8702-Q1 , DRV8703-Q1

PRODUCTION DATA

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机械数据 (封装 | 引脚)

RHB|32

散热焊盘机械数据 (封装 | 引脚)

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7.6 Register Maps

Table 7-14 DRV8703-Q1 Memory Map

Register Name	7	6	5	4	3	2	1	0	Access Type	Address (Hex)
FAULT Status	FAULT	WDFLT	GDF	OCP	VM_UVFL	VCP_UVFL	OTSD	OTW	R	0
VDS and GDF	H2_GDF	L2_GDF	H1_GDF	L1_GDF	H2_VDS	L2_VDS	H1_VDS	L1_VDS	R	1
Main	RESERVED		LOCK			IN1/PH	IN2/EN	CLR_FLT	RW	2
IDRIVE and WD	TDEAD		WD_EN	WD_DLY		IDRIVE			RW	3
VDS	SO_LIM	VDS			DIS_H2_VDS	DIS_L2_VDS	DIS_H1_VDS	DIS_L1_VDS	RW	4
Config	TOFF		CHOP_IDS	VREF_SCL		SH_EN	GAIN_CS		RW	5

Table 7-15 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write

7.6.1 Status Registers

The status registers are used to report warning and fault conditions. Status registers are read only registers.

#GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X9788 lists the memory-mapped registers for the status registers. All register offset addresses not listed in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X9788 should be considered as reserved locations and the register contents should not be modified.

Table 7-16 Status Registers Summary Table

Address	Register Name	Section
0x00h	FAULT status	Go
0x01h	VDS and GDF status	Go

7.6.2 FAULT Status Register (address = 0x00h)

FAULT status is shown in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X5840 and described in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X8906.

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Read only

Figure 7-19 FAULT Status Register

7	6	5	4	3	2	1	0
FAULT	WDFLT	GDF	OCP	VM_UVFL	VCP_UVFL	OTSD	OTW
R-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R-0b

Table 7-17 FAULT Status Field Descriptions

Bit	Field	Type	Default	Description
7	FAULT	R	0b	Logic OR of the FAULT status register excluding the OTW bit
6	WDFLT	R	0b	Watchdog time-out fault
5	GDF	R	0b	Indicates gate drive fault condition
4	OCP	R	0b	Indicates VDS monitor overcurrent fault condition
3	VM_UVFL	R	0b	Indicates VM undervoltage lockout fault condition
2	VCP_UVFL	R	0b	Indicates charge-pump undervoltage fault condition
1	OTSD	R	0b	Indicates overtemperature shutdown
0	OTW	R	0b	Indicates overtemperature warning

7.6.3 VDS and GDF Status Register Name (address = 0x01h)

VDS and GDF status is shown in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X6705 and described in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X8578.

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Read only

Figure 7-20 VDS and GDF Status Register

7	6	5	4	3	2	1	0
H2_GDF	L2_GDF	H1_GDF	L1_GDF	H2_VDS	L2_VDS	H1_VDS	L1_VDS
R-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R-0b	R-0b

Table 7-18 VDS and GDF Status Field Descriptions

Bit	Field	Type	Default	Description
7	H2_GDF	R	0b	Indicates gate drive fault on the high-side FET of half-bridge 2
6	L2_GDF	R	0b	Indicates gate drive fault on the low-side FET of half-bridge 2
5	H1_GDF	R	0b	Indicates gate drive fault on the high-side FET of half-bridge 1
4	L1_GDF	R	0b	Indicates gate drive fault on the low-side FET of half-bridge 1
3	H2_VDS	R	0b	Indicates VDS monitor overcurrent fault on the high-side FET of half-bridge 2
2	L2_VDS	R	0b	Indicates VDS monitor overcurrent fault on the low-side FET of half-bridge 2
1	H1_VDS	R	0b	Indicates VDS monitor overcurrent fault on the high-side FET of half-bridge 1
0	L1_VDS	R	0b	Indicates VDS monitor overcurrent fault on the low-side FET of half-bridge 1

7.6.4 Control Registers

The control registers are used to configure the device. Control registers are read and write capable.

#GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X8360 lists the memory-mapped registers for the status registers. All register offset addresses not listed in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X8360 should be considered as reserved locations and the register contents should not be modified.

Table 7-19 Status Registers Summary Table

Address	Register Name	Section
0x02h	Main control	Go
0x03h	IDRIVE and WD control	Go
0x04h	VDS control	Go
0x05h	Config control	Go

7.6.5 Main Control Register Name (address = 0x02h)

Main control is shown in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X2233 and described in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X7029.

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Read and write

Figure 7-21 Main Control Register

7	6	5	4	3	2	1	0
RESERVED		LOCK			IN1/PH	IN2/EN	CLR_FLT
R/W-00b		R/W-011b			R/W-0b	R/W-0b	R/W-0b

Table 7-20 Main Control Field Descriptions

Bit	Field	Type	Default	Description
7-6	RESERVED	R/W	00b	Reserved
5-3	LOCK	R/W	011b	Write 110b to lock the settings by ignoring further register changes except to address 0x02h. Writing any sequence other than 110b has no effect when unlocked. Write 011b to this register to unlock all registers. Writing any sequence other than 011b has no effect when locked.
2	IN1/PH	R/W	0b	This bit is ORed with the IN1/PH pin
1	IN2/EN	R/W	0b	This bit is ORed with the IN2/EN pin
0	CLR_FLT	R/W	0b	Write a 1 to this bit to clear the fault bits

7.6.6 IDRIVE and WD Control Register Name (address = 0x03h)

IDRIVE and WD control is shown in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X2196 and described in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X197.

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Read and write

Figure 7-22 IDRIVE and WD Register

7	6	5	4	3	2	1	0
TDEAD		WD_EN	WD_DLY		IDRIVE
R/W-00b		R/W-0b	R/W-00b		R/W-111b

Table 7-21 IDRIVE and WD Field Descriptions

Bit	Field	Type	Default	Description
7-6	TDEAD	R/W	00b	Dead time 00b = 120 ns 01b = 240 ns 10b = 480 ns 11b = 960 ns
5	WD_EN	R/W	0b	Enables or disables the watchdog time (disabled by default)
4-3	WD_DLY	R/W	00b	Watchdog timeout delay (if WD_EN = 1) 00b = 10 ms 01b = 20 ms 10b = 50 ms 11b = 100 ms
2-0	IDRIVE	R/W	111b	Sets the peak source current and peak sink current of the gate drive. #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/T4605616-33 lists the bit settings.

Table 7-22 IDRIVE Bit Settings

Bit Value	Source Current		Sink Current
Bit Value	V_VM = 5.5 V	V_VM = 13.5 V	V_VM = 5.5 V	V_VM = 13.5 V
000b	High-side: 10 mA Low-side: 10 mA	High-side: 10 mA Low-side: 10 mA	High-side: 20 mA Low-side: 20 mA	High-side: 20 mA Low-side: 20 mA
001b	High-side: 20 mA Low-side: 20 mA	High-side: 20 mA Low-side: 20 mA	High-side: 40 mA Low-side: 40 mA	High-side: 40 mA Low-side: 40 mA
010b	High-side: 50 mA Low-side: 40 mA	High-side: 50 mA Low-side: 45 mA	High-side: 90 mA Low-side: 85 mA	High-side: 95 mA Low-side: 95 mA
011b	High-side: 70 mA Low-side: 55 mA	High-side: 70 mA Low-side: 60 mA	High-side: 120 mA Low-side: 115 mA	High-side: 130 mA Low-side: 125 mA
100b	High-side: 100 mA Low-side: 75 mA	High-side: 105 mA Low-side: 90 mA	High-side: 170 mA Low-side: 160 mA	High-side: 185 mA Low-side: 180 mA
101b	High-side: 145 mA Low-side: 115 mA	High-side: 155 mA Low-side: 130 mA	High-side: 250 mA Low-side: 235 mA	High-side: 265 mA Low-side: 260 mA
110b	High-side: 190 mA Low-side: 145 mA	High-side: 210 mA Low-side: 180 mA	High-side: 330 mA Low-side: 300 mA	High-side: 350 mA Low-side: 350 mA
111b	High-side: 240 mA Low-side: 190 mA	High-side: 260 mA Low-side: 225 mA	High-side: 420 mA Low-side: 360 mA	High-side: 440 mA Low-side: 430 mA

7.6.7 VDS Control Register Name (address = 0x04h)

VDS control is shown in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X5279 and described in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X3565.

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Read and write

Figure 7-23 VDS Control Register

7	6	5	4	3	2	1	0
SO_LIM	VDS			DIS_H2_VDS	DIS_L2_VDS	DIS_H1_VDS	DIS_L1_VDS
R/W-0b	R/W-111b			R/W-0b	R/W-0b	R/W-0b	R/W-0b

Table 7-23 VDS Control Field Descriptions

Bit	Field	Type	Default	Description
7	SO_LIM	R/W	0b	0b = Default operation 1b = SO output is voltage-limited to 3.6 V
6-4	VDS	R/W	111b	Sets the V_DS(OCP) monitor for each FET 000b = 0.06 V 001b = 0.145 V 010b = 0.17 V 011b = 0.2 V 100b = 0.12 V 101b = 0.24 V 110b = 0.48 V 111b = 0.96 V
3	DIS_H2_VDS	R/W	0b	Disables the VDS monitor on the high-side FET of half-bridge 2 (enabled by default)
2	DIS_L2_VDS	R/W	0b	Disables the VDS monitor on the low-side FET of half-bridge 2 (enabled by default)
1	DIS_H1_VDS	R/W	0b	Disables the VDS monitor on the high-side FET of half-bridge 1 (enabled by default)
0	DIS_L1_VDS	R/W	0b	Disables the VDS monitor on the low-side FET of half-bridge 1 (enabled by default)

7.6.8 Config Control Register Name (address = 0x05h)

Config control is shown in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X5528 and described in #GUID-2C6DE6CE-CF0F-4977-852C-FC365495E21F/X566.

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Read and write

Figure 7-24 Config Control Register

7	6	5	4	3	2	1	0
TOFF		CHOP_IDS	VREF_SCL		SH_EN	GAIN_CS
R/W-00b		R/W-0b	R/W-00b		R/W-0b	R/W-01b

Table 7-24 Config Control Field Descriptions

Bit	Field	Type	Default	Description
7-6	TOFF	R/W	00b	Off time for PWM current chopping 00b = 25 µs 01b = 50 µs 10b = 100 µs 11b = 200 µs
5	CHOP_IDS	R/W	0b	Disables current regulation (enabled by default)
4-3	VREF_SCL	R/W	00b	Scale factor for the VREF input 00b = 100% 01b = 75% 10b = 50% 11b = 25%
2	SH_EN	R/W	0b	Enables sample and hold operation of the shunt amplifier (disabled by default)
1-0	GAIN_CS	R/W	01b	Shunt amplifier gain setting 00b = 10 V/V 01b = 19.8 V/V 10b = 39.4 V/V 11b = 78 V/V