ZHCSG08E October 2016 – January 2021 DRV8702-Q1 , DRV8703-Q1
PRODUCTION DATA
An MCU watchdog function can be enabled to ensure that the external controller that is instructing the DRV8703-Q1 device is active and in a known state. The SPI watchdog must be enabled by writing a 1 to the WD_EN bit through the SPI (disabled by default, bit is 0). When the watchdog is enabled, an internal timer starts to count down to an interval set by the WD_DLY bits. The register address 0x00 must be read by the MCU within the interval set by the WD_DLY bit to reset the watchdog. If the timer is allowed to expire, the nWDFLT pin is enabled. When the nWDFLT pin is enabled the following occurs:
The WDFLT bit remains asserted, and operation is halted until the CLR_FLT bit has been written to 1.
#GUID-D09DB217-2F6C-45B9-B58A-E43D5514FB64/T4605616-55 lists the fault responses of the device under the fault conditions.
| FAULT | CONDITION | H-BRIDGE | CHARGE PUMP | AVDD | DVDD | RECOVERY |
|---|---|---|---|---|---|---|
| VM undervoltage (UVLO) | VVM ≤ V(UVLOx) (5.45 V, max) | Disabled | Disabled | Disabled | Operating | VVM ≥ V(UVLOx) (5.65 V, max) |
| VCP undervoltage (CPUV) | VVCP ≤ V(CP_UV) (VVM + 1.5, typ) | Disabled | Operating | Operating | Operating | VVCP ≥ V(CP_UV) (VVM + 1.5, typ) |
| External FET overload (OCP) | VDS ≥ VDS(OCP) VSP – VSN > 1 V | Disabled | Operating | Operating | Operating | t(RETRY) |
| Gate driver fault (GDF) | Gate voltage unchanged after t(DRIVE) | Disabled | Operating | Operating | Operating | t(RETRY) |
| Watchdog fault (WDFLT) | Watchdog timer expires | Disabled | Operating | Operating | Operating | CLR_FLT bit |
| Thermal shutdown (TSD) | TJ ≥ TSD (150°C, min) | Disabled | Disabled | Disabled | Operating | TJ ≤ TSD – Thys (Thys is typically 20°C) |