ZHCSEB6 October   2015 DRV8704

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Motor Drivers
      2. 7.3.2  Direct PWM Input Mode (Dual Brushed DC Gate Driver)
      3. 7.3.3  Current Regulation
      4. 7.3.4  Decay Modes
      5. 7.3.5  Blanking Time
      6. 7.3.6  Gate Drivers
      7. 7.3.7  Configuring Gate Drivers
      8. 7.3.8  External FET Selection
      9. 7.3.9  Protection Circuits
        1. 7.3.9.1 Overcurrent Protection (OCP)
        2. 7.3.9.2 Gate Driver Fault (PDF)
        3. 7.3.9.3 Thermal Shutdown (TSD)
        4. 7.3.9.4 Undervoltage Lockout (UVLO)
      10. 7.3.10 Serial Data Format
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 Control Registers
        1. 7.5.1.1 CTRL Register (Address = 0x00h)
        2. 7.5.1.2 TORQUE Register (Address = 0x01h)
        3. 7.5.1.3 OFF Register (Address = 0x02h)
        4. 7.5.1.4 BLANK Register (Address = 0x03h)
        5. 7.5.1.5 DECAY Register (Address = 0x04h)
        6. 7.5.1.6 Reserved Register Address = 0x05h
        7. 7.5.1.7 DRIVE Register Address = 0x06h
        8. 7.5.1.8 STATUS Register (Address = 0x07h)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 Current Chopping Configuration
        4. 8.2.2.4 Decay Modes
        5. 8.2.2.5 Sense Resistor
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV8704 is used in brushed DC motor control.

8.2 Typical Application

The following design procedure can be used to configure the DRV8704.

DRV8704 typ_app_lvsd29.gif Figure 18. Dual Brushed-DC Motor Control

8.2.1 Design Requirements

Table 12 shows design input parameters for system design.

Table 12. Design Parameters

DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Supply voltage VM 24 V
FET total gate charge (1) Qg 41 nC (typically)
FET gate-to-drain charge (1) Qgd 6.7 nC (typically)
Target FET gate rise time RT 20 to 100 ns
Motor winding resistance RL 400 mΩ
Motor winding inductance LL 258 μH
Target chopping current ICHOP 5.5 A
(1) FET part number is CSD18540Q5B

8.2.2 Detailed Design Procedure

8.2.2.1 External FET Selection

The DRV8704 FET support is based on the charge pump capacity and output PWM frequency. For a quick calculation of FET driving capacity, use the following equations when drive and brake (slow decay) are the primary modes of operation:

Equation 5. DRV8704 eq_03_Qg_lvsd29.gif

where

  • ƒPWM is the maximum desired PWM frequency to be applied to the DRV8704 inputs or the current chopping frequency, whichever is larger.
  • IVCP is the charge pump capacity, which is 20 mA.

The factor of two arises because there are two H-bridges present.

The current chopping frequency is at most:

Equation 6. DRV8704 eq_04_fPWM_lvsd29.gif

Example:

If a system uses a maximum PWM frequency of 40 kHz, then the DRV8704 will support Qg < 250 nC FETs.

If the application will require a forced fast decay (or alternating between drive and reverse drive), the maximum FET driving capacity is given by:

Equation 7. DRV8704 eq_05_Qg_lvsd29.gif

8.2.2.2 IDRIVE Configuration

IDRIVE is selected based on the gate charge of the FETs. The IDRIVEx and TDRIVEx registers need to be configured so that the FET gates are charged completely during TDRIVE. If IDRIVE is chosen to be too low for a given FET, or if TDRIVE is less than the intended rise time, then the FET may not turn on completely. TI suggests to adjust these values in-system with the required external FETs and motor to determine the best possible setting for any application.

For FETs with a known gate-to-drain charge Qgd and desired rise time RT, IDRIVE and TDRIVE can be selected based on:

Equation 8. DRV8704 eq_06_IDRIVE_lvsd29.gif
Equation 9. TDRIVE > 2 × RT

Example:

If the gate-to-drain charge is 5.9 nC, and the desired rise time is around 20 to 100 ns:

IDRIVE1 = 6.7 nC / 20 ns = 335 mA

IDRIVE2 = 6.7 nC / 100 ns = 67 mA

Select IDRIVE between 67 and 335 mA.

We select IDRIVEP as 200-mA source and IDRIVEP as 400-mA sink.

We select TDRIVEN and TDRIVEP as 525 ns.

8.2.2.3 Current Chopping Configuration

The chopping current is set based on the sense resistor value, shunt amplifier gain set by the ISGAIN register, and the TORQUE register setting. The following is used to calculate the current:

Equation 10. DRV8704 eq_07_Ichop_lvsd29.gif

Example:

If the desired chopping current is 5.5 A:

Set RSENSE = 100 mΩ.

Set ISGAIN to the 5 V/V setting.

The TORQUE register can be (decimal) 255.

8.2.2.4 Decay Modes

The DRV8704 supports several different decay modes: slow decay, fast decay, mixed decay, and automatic mixed decay. The current through the motor windings is regulated using an adjustable fixed-time-off scheme. This means that after any drive phase, when a motor winding current has hit the current chopping threshold (ITRIP), the DRV8704 will place the winding in one of the decay modes for TOFF. After TOFF, a new drive phase starts.

8.2.2.5 Sense Resistor

For optimal performance, it is important for the sense resistor to be:

  • Surface-mount
  • Low inductance
  • Rated for high enough power
  • Placed closely to the motor driver

The power dissipated by the sense resistor equals IRMS 2 × R. For example, if peak motor current is 3 A, RMS motor current is 2 A, and a 0.05-Ω sense resistor is used, the resistor will dissipate 2 A2 × 0.05 Ω = 0.2 W. The power quickly increases with higher current levels.

Resistors typically have a rated power within some ambient temperature range, along with a derated power curve for high ambient temperatures. When a PCB is shared with other components generating heat, margin should be added. It is always best to measure the actual sense resistor temperature in a final system, along with the power MOSFETs, as those are often the hottest components.

Because power resistors are larger and more expensive than standard resistors, it is common practice to use multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat dissipation.

8.2.3 Application Curves

DRV8704 app_01.gif
Figure 19. Current Regulation
DRV8704 app_04.gif
Figure 20. Motor Startup