The device integrates a programmable window type SPI watchdog timer to verify that the external controller is operating and the SPI bus integrity is monitored. The SPI watchdog timer can be enabled by through the WD_EN SPI register bit. The watchdog timer is disabled by default. When the watchdog timer is enabled, an internal timer starts to count up. The watcher dog timer is reset by inverting the WD_RST SPI register.. This WD_RST must be issued between the lower window time and the upper window time. If a watchdog timer fault is detected, the device response can be configured to either report only a warning or report a fault and disabled the half-bridge drivers. If the watchdog is set to disable the half-bridges drivers, the drivers will be reenabled after a CLR_FLT command is sent to remove the watchdog fault condition.