Bypass the PVDD pin to the GND pin using a low-ESR ceramic bypass capacitor with a recommended value of 0.1 µF. Place this capacitor as close to the PVDD pin as possible with a thick trace or ground plane connected to the GND pin. Additionally, bypass the PVDD pin using a bulk capacitor rated for PVDD. This component can be electrolytic. This capacitance must be at least 10 µF. It is acceptable if this capacitance is shared with the bulk capacitance for the external power MOSFETs.

Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk capacitance should be placed such that it minimizes the length of any high current paths through the external MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.

Place a low-ESR ceramic capacitor between the CPL1 / CPH1 and CPL2 / CP2H pins. The CP1 capacitor should be 0.1 µF, rated for PVDD, and be of type X5R or X7R. The CP2 capacitor should be 0.1 µF, rated for PVDD + 16 V, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and PVDD pins. This capacitor should be 1 µF, rated for 16 V, and be of type X5R or X7R.

Bypass the DVDD pin to the DGND pin with a 1.0 µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R or X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the DGND pin. Bypass the AREF pin to the AGND pin with a 0.1 µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R or X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the AGND pin. If local bypass capacitors are already present on these power supplies in close proximity of the device to minimize noise, these additional components for DVDD and/or AREF are not required.

The DRAIN pin can be shorted directly to the PVDD pin. However, if a significant distance is between the device and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side external MOSFETs. Ensure the PGNDx pins have a low impedance path to the sources of the low-side external MOSFETs and to the PCB GND plane.. pins directly to the GND plane. These recommendations allow for more accurate VDS sensing of the external MOSFETs for overcurrent detection.

Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the low-side MOSFET source back to the PGNDx pin.