ZHCSCS1D June 2014 – November 2020 DRV8801A-Q1
PRODUCTION DATA
The following table shows the logic for the DRV8801A-Q1:
| nSLEEP | PHASE | ENABLE | MODE1 | MODE2 | OUTA | OUTB | OPERATION |
|---|---|---|---|---|---|---|---|
| 0 | X | X | X | X | Z | Z | Sleep mode |
| 1 | 0 | 1 | X | X | L | H | Reverse |
| 1 | 1 | 1 | X | X | H | L | Forward |
| 1 | 0 | 0 | 0 | X | H | L | Fast decay |
| 1 | 1 | 0 | 0 | X | L | H | Fast decay |
| 1 | X | 0 | 1 | 0 | L | L | Low-side Slow decay |
| 1 | X | 0 | 1 | 1 | H | H | High-side Slow decay |
To prevent reversal of current during fast-decay synchronous rectification, outputs go to the high impedance state as the current approaches 0 A.
The path of current flow for each of the states in the above logic table is shown in GUID-0A53539C-6806-43FB-8D31-349DAF153A9B.html#SLVSC798151.