SLVS997G October 2009 – October 2015 DRV8812
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息
5 Pin Configuration and Functions
PWP Package
28 Pin HTSSOP
Top View
RHD Package
28-Pin VQFN
Top View
Pin Functions
| PIN | I/O(1) | DESCRIPTION | EXTERNAL COMPONENTS OR CONNECTIONS |
||
|---|---|---|---|---|---|
| NAME | PWP | RHD | |||
| POWER AND GROUND | |||||
| GND | 14, 28 | 3, 17 | - | Device ground | |
| VMA | 4 | 7 | - | Bridge A power supply | Connect to motor supply (8.2-V to 45-V). Both pins must be connected to the same supply, bypassed with a 0.1uF capacitor to GND, and connected to appropriate bulk capacitance. |
| VMB | 11 | 14 | - | Bridge B power supply | |
| V3P3OUT | 15 | 18 | O | 3.3-V regulator output | Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Can be used to supply VREF. |
| CP1 | 1 | 4 | IO | Charge pump flying capacitor | Connect a 0.01-μF 50-V capacitor between CP1 and CP2. |
| CP2 | 2 | 5 | IO | Charge pump flying capacitor | |
| VCP | 3 | 6 | IO | High-side gate drive voltage | Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ resistor to VM. |
| CONTROL | |||||
| AENBL | 21 | 24 | I | Bridge A enable | Logic high to enable bridge A |
| APHASE | 20 | 23 | I | Bridge A phase (direction) | Logic high sets AOUT1 high, AOUT2 low |
| AI0 | 24 | 27 | I | Bridge A current set | Sets bridge A current: 00 = 100%, 01 = 71%, 10 = 38%, 11 = 0 |
| AI1 | 25 | 28 | I | ||
| BENBL | 22 | 25 | I | Bridge B enable | Logic high to enable bridge B |
| BPHASE | 23 | 26 | I | Bridge B phase (direction) | Logic high sets BOUT1 high, BOUT2 low |
| BI0 | 26 | 1 | I | Bridge B current set | Sets bridge B current: 00 = 100%, 01 = 71%, 10 = 38%, 11 = 0 |
| BI1 | 27 | 2 | I | ||
| DECAY | 19 | 22 | I | Decay mode | Low = slow decay, open = mixed decay, high = fast decay |
| nRESET | 16 | 19 | I | Reset input | Active-low reset input initializes internal logic and disables the H-bridge outputs |
| nSLEEP | 17 | 20 | I | Sleep mode input | Logic high to enable device, logic low to enter low-power sleep mode |
| AVREF | 12 | 15 | I | Bridge A current set reference input | Reference voltage for winding current set. Can be driven individually with an external DAC for microstepping, or tied to a reference (e.g., V3P3OUT). A 0.01-µF bypass capacitor to GND is recommended. |
| BVREF | 13 | 16 | I | Bridge B current set reference input | |
| STATUS | |||||
| nFAULT | 18 | 21 | OD | Fault | Logic low when in fault condition (overtemp, overcurrent) |
| OUTPUT | |||||
| ISENA | 6 | 9 | IO | Bridge A ground / Isense | Connect to current sense resistor for bridge A |
| ISENB | 9 | 12 | IO | Bridge B ground / Isense | Connect to current sense resistor for bridge B |
| AOUT1 | 5 | 8 | O | Bridge A output 1 | Connect to motor winding A |
| AOUT2 | 7 | 10 | O | Bridge A output 2 | |
| BOUT1 | 10 | 13 | O | Bridge B output 1 | Connect to motor winding B |
| BOUT2 | 8 | 11 | O | Bridge B output 2 | |
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output