SLVSA72E April 2010 – October 2015 DRV8813
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7 Detailed Description
7.1 Overview
The DRV8813 is an integrated motor driver solution for a bipolar stepper motor or two brushed DC motors. The device integrates two NMOS H-bridges, current sense, regulation circuitry, and detailed fault detection. The DRV8813 can be powered with a supply voltage from 8.2 V to 45 V, and is capable of providing an output current up to 2.5 A full-scale.
A PHASE/ENBL interface allows for simple interfacing to the controller circuit. The winding current control allows the external controller to adjust the regulated current that is provided to the motor. The current regulation is highly configurable, with three decay modes of operation. Fast, slow, and mixed decay can be selected depending on the application requirements.
A low-power sleep mode is included, which allows the system to save power when not driving the motor.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 PWM Motor Drivers
The DRV8813 contains two H-bridge motor drivers with current-control PWM circuitry. Figure 5 shows a block diagram of the motor control circuitry. A bipolar stepper motor is shown, but the drivers can also drive two separate DC motors.
Figure 5. Motor Control Circuitry
There are multiple VM motor power supply pins. All VM pins must be connected together to the motor supply voltage.
7.3.2 Protection Circuits
The DRV8813 is fully protected against undervoltage, overcurrent and overtemperature events.
7.3.2.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge disables and the nFAULT pin drives low. The device remains disabled until either nRESET pin is applied, or VM is removed and reapplied.
Overcurrent conditions on both high and low side devices; that is, a short to ground, supply, or across the motor winding results in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage.
7.3.2.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge disables and the nFAULT pin drives low. Once the die temperature has fallen to a safe level, operation automatically resumes.
7.3.2.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the device is disabled and internal logic resets. Operation resumes when VM rises above the UVLO threshold.
7.4 Device Functional Modes
7.4.1 Bridge Control
The xPHASE input pins control the direction of current flow through each H-bridge. The xENBL input pins enable the H-bridge outputs when active high. Table 1 shows the logic.
Table 1. H-Bridge Logic
| xENBL | xPHASE | xOUT1 | xOUT2 |
|---|---|---|---|
| 0 | X | Z | Z |
| 1 | 1 | H | L |
| 1 | 0 | L | H |
The control inputs have internal pulldown resistors of approximately 100 kΩ.
7.4.2 Current Regulation
The current through the motor windings is regulated by a fixed-frequency PWM current regulation, or current chopping. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the current until the beginning of the next PWM cycle.
For stepping motors, current regulation is normally used at all times, and can changing the current can be used to microstep the motor. For DC motors, current regulation is used to limit the start-up and stall current of the motor.
If the current regulation feature is not needed, it can be disabled by connecting the xISENSE pins directly to ground and connecting the xVREF pins to V3P3.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input from the xVREF pins, and is scaled by a 2-bit DAC that allows current settings of 100%, 71%, 38% of full-scale, plus zero.
The full-scale (100%) chopping current is calculated in Equation 1.
Example:
If a 0.25-Ω sense resistor is used and the VREFx pin is 2.5 V, the full-scale (100%) chopping current is 2.5 V / (5 × 0.25 Ω) = 2 A.
Two input pins per H-bridge (xI1 and xI0) are used to scale the current in each bridge as a percentage of the full-scale current set by the VREF input pin and sense resistance. The xI0 and xI1 pins have internal pulldown resistors of approximately 100 kΩ. The function of the pins is shown in Table 2.
Table 2. H-Bridge Pin Functions
| xI1 | xI0 | RELATIVE CURRENT (% FULL-SCALE CHOPPING CURRENT) |
|---|---|---|
| 1 | 1 | 0% (Bridge disabled) |
| 1 | 0 | 38% |
| 0 | 1 | 71% |
| 0 | 0 | 100% |
When both xI bits are 1, the H-bridge is disabled and no current flows.
Example:
If a 0.25-Ω sense resistor is used and the VREF pin is 2.5 V, the chopping current is 2 A at the 100% setting (xI1, xI0 = 00). At the 71% setting (xI1, xI0 = 01) the current is 2 A × 0.71 = 1.42 A, and at the 38% setting (xI1, xI0 = 10) the current is 2 A × 0.38 = 0.76 A. If (xI1, xI0 = 11) the bridge disables and no current flows.
7.4.3 Decay Mode
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 6 as case 1. The current flow direction shown indicates the state when the xENBL pin is high.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 6 as case 2.
In slow decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge. This is shown in Figure 6 as case 3.
Figure 6. Decay Mode
The DRV8813 supports fast decay, slow decay, and a mixed decay mode. Slow, fast, or mixed decay mode is selected by the state of the DECAY pin - logic low selects slow decay, open selects mixed decay operation, and logic high sets fast decay mode. The DECAY pin has both an internal pullup resistor of approximately 130 kΩ and an internal pulldown resistor of approximately 80 kΩ. This sets the mixed decay mode if the pin is left open or undriven. The DECAY pin sets the decay mode for both H-bridges.
Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow decay mode for the remainder of the fixed PWM period.
7.4.4 Blanking Time
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. The blanking time also sets the minimum on time of the PWM.
7.4.5 nRESET and nSLEEP Operation
The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge drivers. All inputs are ignored while nRESET is active.
Driving nSLEEP low puts the device into a low power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In this state, all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (approximately 1 ms) must to pass before the motor driver becomes fully operational. The nRESET and nSLEEP have internal pulldown resistors of approximately 100 kΩ. These signals must be driven to logic high for device operation.