7.3.1 PWM Motor Drivers

The DRV8823-Q1 device contains four H-bridge motor drivers with current-control PWM circuitry. A block diagram showing drivers A and B of the motor control circuitry (as typically used to drive a bipolar stepper motor) is shown in Figure 11. Drivers C and D are the same as A and B (though the R_DS(ON) of the output FETs is different).

Figure 11. Motor Driver Circuit

Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor supply voltage.

7.3.2 Protection Circuits

The DRV8823-Q1 device is fully protected against undervoltage, overcurrent, and overtemperature events.

7.4.1 Bridge Control

The xENBL bits in the serial interface registers enable current flow in each H-bridge when set to 1.

The xPHASE bits in the serial interface registers control the direction of current flow through each H-bridge. Table 1 shows the logic.

7.4.2 Current Regulation

The motor driver employs fixed-frequency PWM current regulation (also called current chopping). When a winding is activated, the current through it rises until it reaches a threshold, then the current is switched off until the next PWM period.

The PWM frequency is fixed at 50 kHz, but it may also be set to 100 kHz through the factory option.

The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input from the VREF pin.

The full-scale (100%) chopping current is calculated as follows:

Equation 1.

Example:

If a 0.5-Ω sense resistor is used and the V_REFx pin is 2.5 V, the full-scale (100%) chopping current is:
2.5 V/(5 × 0.5 Ω) = 1 A.

Three serial interface register bits per H-bridge (xI2, xI1 and xI0) are used to scale the current in each bridge as a percentage of the full-scale current set by the VREF input pin and sense resistance. The function of the bits is shown in Table 2.

7.4.3 Decay Mode

During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 12 as case 1. The current flow direction shown indicates positive current flow in Figure 12.

Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay.

In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 12 as case 2.

In slow decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge. This is shown in Figure 12 as case 3.

Figure 12. Decay Mode

The DRV8823-Q1 device supports slow decay and a mixed decay mode. Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow decay mode for the remainder of the fixed PWM period.

Slow or mixed decay mode is selected by the state of the xDECAY bits in the serial interface registers. If the xDECAY bit is 0, slow decay is selected. If the xDECAY bit is 1, mixed decay is selected.

7.4.4 Blanking Time

After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also sets the minimum on time of the PWM.

7.5.1 Serial Data Transmission

Data transfers consist of 16 bits of serial data, shifted into the SDATA pin LSB first.

On serial writes to the DRV8823-Q1 device, additional clock edges following the final data bit continues to shift data bits into the data register; therefore, the last 16 bits presented are latched and used.

One of two registers is selected by setting bits in an address field in the four upper bits in the serial data transferred (ADDR in the tables below). One 16-bit register is used to control motor number 1 (bridges A and B), and a second 16-bit register is used to control motor 2 (bridges C and D).

Data can only be transferred into the serial interface if the SCS input pin is active high.

Data is initially clocked in to a temporary holding register. This data is latched into the motor driver on the rising edge of the SSTB pin. If the SSTB pin is tied high at all times, the data will be latched in after all 16 bits have been transferred.

Table 3. Motor 1 Command (Bridges A and B)

Table 4. Motor 2 Command (Bridges C and D)