SLVSBW9C April 2013 – December 2015 DRV8832-Q1
PRODUCTION DATA.
请参考 PDF 数据表获取器件具体的封装图。
The IN1 and IN2 control pins enable the H-bridge outputs. The following table shows the logic:
| IN1 | IN2 | OUT1 | OUT2 | Function |
|---|---|---|---|---|
| 0 | 0 | Z | Z | Sleep/coast |
| 0 | 1 | L | H | Reverse |
| 1 | 0 | H | L | Forward |
| 1 | 1 | H | H | Brake |
When both bits are zero, the output drivers are disabled and the device is placed into a low-power sleep state. The current limit fault condition (if present) is also cleared. Note that when transitioning from either brake or sleep mode to forward or reverse, the voltage control PWM starts at zero duty cycle. The duty cycle slowly ramps up to the commanded voltage. This can take up to 12 ms to go from sleep to 100% duty cycle. Because of this, high-speed PWM signals cannot be applied to the IN1 and IN2 pins. To control motor speed, use the VSET pin as described in the following paragraph.
Because of the sleep mode functionality described previously, when applying an external PWM to the DRV8832-Q1, hold one input logic high while applying a PWM signal to the other. If the logic input is held low instead, then the device will cycle in and out of sleep mode, causing the FAULTn pin to pulse low on every sleep mode exit.