SLVSB17D March 2012 – April 2016 DRV8836
PRODUCTION DATA.
7 Detailed Description
7.1 Overview
The DRV8836 is an integrated motor driver solution used for brushed motor control. The device integrates two
H-bridges, and can drive two DC motor or one stepper motor. The output driver block for each H-bridge consists of N-channel power MOSFETs. An internal charge pump generates the gate drive voltages. Protection features include overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature protection.
The bridges connect in parallel for additional current capability.
The mode pin allows selection of either a PHASE/ENABLE or IN/IN interface.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Sleep Mode
If the nSLEEP pin enters a logic-low state, the DRV8836 enters a low-power sleep mode. In this state all unnecessary internal circuitry is powered down.
7.3.2 Power Supplies and Input Pins
There is a weak pulldown resistor (approximately 100 kΩ) to ground on the input pins.
7.3.3 Protection Circuits
The DRV8836 is fully protected against undervoltage, overcurrent, and overtemperature events.
7.3.3.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge disable. After approximately
1 ms, the bridge re-enables automatically.
Overcurrent conditions on both high and low side devices, like a short to ground, supply, or across the motor winding results in an overcurrent shutdown.
7.3.3.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge disable. Once the die temperature has fallen to a safe level operation automatically resumes.
7.3.3.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VCC pins falls below the undervoltage lockout threshold voltage, all circuitry in the device disables, and internal logic resets. Operation resumes when VCC rises above the UVLO threshold.
Table 1. Device Protection
| FAULT | CONDITION | ERROR REPORT | H-BRIDGE | INTERNAL CIRCUITS | RECOVERY |
|---|---|---|---|---|---|
| VCC undervoltage (UVLO) | VCC < VUVLO | None | Disabled | Disabled | VCC > VUVLO |
| Overcurrent (OCP) | IOUT > IOCP | None | Disabled | Operating | tOCR |
| Thermal shutdown (TSD) | TJ > TTSD | None | Disabled | Operating | TJ < TTSD – THYS |
7.4 Device Functional Modes
The DRV8836 is active when the nSLEEP pin is set to a logic high. When in sleep mode, the H-bridge FETs disable (Hi-Z).
Table 2. Device Operating Modes
| OPERATING MODE | CONDITION | H-BRIDGE | INTERNAL CIRCUITS |
|---|---|---|---|
| Operating | nSLEEP high | Operating | Operating |
| Sleep mode | nSLEEP low | Disabled | Disabled |
| Fault encountered | Any fault condition met | Disabled | See Table 1 |
7.4.1 Bridge Control
Two control modes are available in the DRV8836: IN/IN mode and PHASE/ENABLE mode. IN/IN mode is selected if the MODE pin is driven low or left unconnected; PHASE/ENABLE mode is selected if the MODE pin is driven to logic high. The following tables show the logic for these modes.
Table 3. IN/IN Mode
| MODE | xIN1 | xIN2 | xOUT1 | xOUT2 | FUNCTION (DC MOTOR) |
|---|---|---|---|---|---|
| 0 | 0 | 0 | Z | Z | Coast |
| 0 | 0 | 1 | L | H | Reverse |
| 0 | 1 | 0 | H | L | Forward |
| 0 | 1 | 1 | L | L | Brake |
Table 4. PHASE/ENABLE Mode
| MODE | xENABLE | xPHASE | xOUT1 | xOUT2 | FUNCTION (DC MOTOR) |
|---|---|---|---|---|---|
| 1 | 0 | X | L | L | Brake |
| 1 | 1 | 1 | L | H | Reverse |
| 1 | 1 | 0 | H | L | Forward |