SLVSBA2D July   2012  – May 2016 DRV8844

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Stage
      2. 7.3.2 Logic Inputs
      3. 7.3.3 Bridge Control
      4. 7.3.4 Charge Pump
      5. 7.3.5 Protection Circuits
        1. 7.3.5.1 Overcurrent Protection (OCP)
        2. 7.3.5.2 Thermal Shutdown (TSD)
        3. 7.3.5.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 nRESET and nSLEEP Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Heatsinking
    4. 10.4 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

PWP Package
28-Pin HTSSOP
Top View
DRV8844 po2_pwp_lvsba2.gif

Pin Functions

PIN TYPE(1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS
NAME NO.
POWER AND GROUND
CP1 1 P Charge pump flying capacitor Connect a 0.01-μF 100-V capacitor between CP1 and CP2.
CP2 2 P Charge pump flying capacitor
LGND 19 P Logic input reference ground Connect to logic ground. This may be any voltage between VNEG and VM – 8 V.
V3P3OUT 15 P 3.3-V regulator output Bypass to VNEG with a 0.47-μF 6.3-V ceramic capacitor. Can be used to supply VREF.
VCP 3 P High-side gate drive voltage Connect a 0.1-μF 16-V ceramic capacitor to VM.
VM 4, 11 P Main power supply Connect to motor supply (8 V to 60 V). Both pins must be connected to same supply. Bypass to VNEG with a 10-µF (minimum) capacitor.
SRC12 6 P Low-side FET source for OUT1 and OUT2 Connect to VNEG directly or through optional current-sense resistor
SRC34 9 P Low-side FET source for OUT3 and OUT4
VNEG 14, 28, PPAD P Negative power supply (dual supplies) or ground (single supply)
CONTROL
EN1 26 I Channel 1 enable Logic high enables OUT1. Internal pulldown.
EN2 24 I Channel 2 enable Logic high enables OUT2. Internal pulldown.
EN3 22 I Channel 3 enable Logic high enables OUT3. Internal pulldown.
EN4 20 I Channel 4 enable Logic high enables OUT4. Internal pulldown.
IN1 27 I Channel 1 input Logic input controls state of OUT1. Internal pulldown.
IN2 25 I Channel 2 input Logic input controls state of OUT2. Internal pulldown.
IN3 23 I Channel 3 input Logic input controls state of OUT3. Internal pulldown.
IN4 21 I Channel 4 input Logic input controls state of OUT4. Internal pulldown.
nRESET 16 I Reset input Active-low reset input initializes internal logic and disables the H-bridge outputs. Internal pulldown.
nSLEEP 17 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown.
STATUS
nFAULT 18 OD Fault Logic low when in fault condition (overtemperature, overcurrent, UVLO). Open-drain output.
OUTPUT
OUT1 5 O Output 1 Connect to loads
OUT2 7 O Output 2
OUT3 8 O Output 3
OUT4 10 O Output 4
NO CONNECT
NC 12, 13 — No connect No connection to these pins
(1) I = input, O = output, OD = open-drain output, P = power
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