ZHCSIO5B October   2017  – January 2021 DRV8873-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control
        1. 7.3.1.1 Control Modes
        2. 7.3.1.2 Half-Bridge Operation
        3. 7.3.1.3 22
        4. 7.3.1.4 Internal Current Sense and Current Regulation
        5. 7.3.1.5 Slew-Rate Control
        6. 7.3.1.6 Dead Time
        7. 7.3.1.7 Propagation Delay
        8. 7.3.1.8 nFAULT Pin
        9. 7.3.1.9 nSLEEP as SDO Reference
      2. 7.3.2 Motor Driver Protection Circuits
        1. 7.3.2.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.2.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.2.3 Overcurrent Protection (OCP)
          1. 7.3.2.3.1 Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.2.3.2 Automatic Retry (OCP_MODE = 01b)
          3. 7.3.2.3.3 Report Only (OCP_MODE = 10b)
          4. 7.3.2.3.4 Disabled (OCP_MODE = 11b)
        4. 7.3.2.4 Open-Load Detection (OLD)
          1. 7.3.2.4.1 Open-Load Detection in Passive Mode (OLP)
          2. 7.3.2.4.2 Open-Load Detection in Active Mode (OLA)
        5. 7.3.2.5 Thermal Shutdown (TSD)
          1. 7.3.2.5.1 Latched Shutdown (TSD_MODE = 0b)
          2. 7.3.2.5.2 Automatic Recovery (TSD_MODE = 1b)
        6. 7.3.2.6 Thermal Warning (OTW)
      3. 7.3.3 Hardware Interface
        1. 7.3.3.1 MODE (Tri-Level Input)
        2. 7.3.3.2 Slew Rate
    4. 7.4 Device Functional Modes
      1. 7.4.1 Motor Driver Functional Modes
        1. 7.4.1.1 Sleep Mode (nSLEEP = 0)
        2. 7.4.1.2 Disable Mode (nSLEEP = 1, DISABLE = 1)
        3. 7.4.1.3 Operating Mode (nSLEEP = 1, DISABLE = 0)
        4. 7.4.1.4 nSLEEP Reset Pulse
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI) Communication
        1. 7.5.1.1 SPI Format
        2. 7.5.1.2 SPI for a Single Slave Device
        3. 7.5.1.3 SPI for Multiple Slave Devices in Parallel Configuration
        4. 7.5.1.4 SPI for Multiple Slave Devices in Daisy Chain Configuration
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Motor Voltage
        2. 8.2.1.2 Drive Current and Power Dissipation
        3. 8.2.1.3 Sense Resistor
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Thermal Considerations
        2. 8.2.2.2 Heatsinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES (VM, DVDD)
VVMVM operating voltage4.538V
IVMVM operating supply currentVVM = 13.5 V; nSLEEP = 1; DISABLE =0510mA
IVM(Q)VM sleep mode supply currentVVM = 13.5 V; nSLEEP = 01530µA
VDVDDInternal logic regulator voltage2-mA load, VVM > 5.5 V4.755.3V
t(SLEEP)Sleep timenSLEEP low to start device shutdown50µs
t(RESET)nSLEEP reset pulsenSLEEP low to only clear fault registers520µs
t(WAKE)Wake-up timenSLEEP high to device ready for input signals1.5ms
tonTurn-on timeVM > V(UVLO); nSLEEP = 1, to output transition1.5ms
t(DISABLE)DISABLE deglitch timeDISABLE signal transition2.5µs
CHARGE PUMP (VCP, CPH, CPL)
VVCPVCP operating voltagewith respect to VMVVM+5V
IVCPVCP currentVVM = 13.5 V710mA
f(VCP)Charge pump switching frequencyVVM > V(UVLO); nSLEEP = 1400kHz
LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, nSLEEP, SCLK, SDI)
VILInput logic-low voltage00.8V
VIHInput logic-high voltage1.65.3V
VHYSInput logic hysteresis150mV
IILInput logic-low currentVIN = 0 V–55µA
IIHInput logic-high currentVIN = 5 V50µA
RPDInternal pulldown resistanceto GND100kΩ
tpdPropagation delay (EN/IN1, PH/IN2 to OUTx = 50%)SR = 000b; IO = 1 A1.2µs
SR = 001b; IO = 1 A1.6
SR = 010b; IO = 1 A2.6
SR = 011b; IO = 1 A3.4
SR = 100b; IO = 1 A4.1
SR = 101b; IO = 1 A5.2
SR = 110b; IO = 1 A7.8
SR = 111b; IO = 1 A13.3
LOGIC-LEVEL INPUT (DISABLE)
RPU,DISInternal pull-up resistanceDISABLE to DVDD100kΩ
VIL,DISInput logic-low voltage00.8V
VIH,DISInput logic-high voltage1.65.3V
LOGIC-LEVEL INPUT (nSCS)
VIL,nSCSInput logic-low voltage00.8V
VIH,nSCSInput logic-high voltage1.65.3V
RPU,nSCSInternal pull-up resistancenSCS to nSLEEP450kΩ
LOGIC-LEVEL INPUT (nSLEEP)
VIL,SLEEPInput logic-low voltage00.8V
VIH,SLEEPInput logic-high voltage2.75.3V
IIH,SLEEPInput logic-high currentVIN = 5 V; nSCS is High80+ISDO(1)µA
THREE-LEVEL INPUT (MODE)
RIN-1Input mode 1Tied to GND105Ω
RIN-2Input mode 2Tied to GND190kΩ
RIN-3Input mode 3Tied to DVDD105Ω
PUSH-PULL OUTPUT (SDO)
RPD,SDOInternal pull-down resistanceWith respect to GND3050Ω
RPU,SDOInternal pull-up resistanceWith respect to nSLEEP120240Ω
OPEN DRAIN OUTPUT (nFAULT)
VOLOutput logic-low voltageIO = 2 mA0.1V
IOZOutput high-impedance leakageVO = 5 V–22µA
MOTOR DRIVER OUTPUTS (OUT1, OUT2)
RDS(ON)High-side FET on-resistanceVVM = 13.5 V; TA = 25°C; TJ = 25°C75mΩ
VVM = 13.5 V; TA = 25°C; TJ = 150°C125155
RDS(ON)Low-side FET on-resistanceVVM = 13.5 V; TA = 25°C; TJ = 25°C75mΩ
VVM = 13.5 V; TA = 25°C; TJ = 150°C125155
t(DEAD)Output dead timeSR = 100b500ns
VF(DIODE)Body diode forward voltageIO = 1 A0.8V
ISINKSink current when OUTx = Hi-ZnSLEEP = 062µA
nSLEEP = 1, DISABLE = 1340
SRSlew rate (H/W Device)
OUTx 10% to 90% changing		IO = 1 A; Connect to GND53.2V/µs
IO = 1 A; R(SR) = 22 kΩ ± 5% to GND34
IO = 1 A; R(SR) = 68 kΩ ± 5% to GND18.3
IO = 1 A; No connect (Hi-Z)13
IO = 1 A; R(SR) = 51 kΩ ± 5% to DVDD7.9
IO = 1 A; Connect to DVDD2.6
SRSlew rate (SPI Device)
OUTx 10% to 90% changing		IO = 1 A; SR = 000b53.2V/µs
IO = 1 A; SR = 001b34
IO = 1 A; SR = 010b18.3
IO = 1 A; SR = 011b13
IO = 1 A; SR = 100b10.8
IO = 1 A; SR = 101b7.9
IO = 1 A; SR = 110b5.3
IO = 1 A; SR = 111b2.6
CURRENT SENSE OUTPUTS (IPROPI1, IPROPI2)
kCurrent mirror scaling1100A/A
kERRCurrent mirror scalingIO < 1 A–5050mA
IO ≥ 1 A–55%
t(IPROPI)OUTx to IPROPIVO = 2 V; SR = 000b2.2µs
VO = 2 V; SR = 111b10.5
CURRENT REGULATION
ITRIPCurrent limit thresholdITRIP_LVL = 00b; VVM = 13.5 V3.273.854.43A
ITRIP_LVL = 01b; VVM = 13.5 V4.65.46.2
ITRIP_LVL = 10b; VVM = 13.5 V5.56.57.5
ITRIP_LVL = 11b; VVM = 13.5 V5.9578.1
tOFFPWM off-timeTOFF = 00b20µs
TOFF = 01b40
TOFF = 10b60
TOFF = 11b80
tBLANKPWM blanking time5µs
PROTECTION CIRCUITS
V(UVLO)VM undervoltage lockoutVM falling; UVLO report4.354.45V
VM rising; UVLO recovery4.54.7
t(UVLO)VM UVLO falling deglitch timeVM falling; UVLO report10µs
V(RST)VM UVLO resetVM falling; UVLO report; device reset4.1V
VVCP(UV)Charge pump undervoltageVVM = 12 V; TA = 25°C; CPUV reportVVM + 2.25V
I(OCP)Overcurrent protection trip level10A
t(OCP)Overcurrent deglitch time35µs
t(RETRY)Overcurrent retry time (H/W Device)4ms
t(RETRY)Overcurrent retry time (SPI Device)OCP_TRETRY = 00b0.5ms
OCP_TRETRY = 01b1
OCP_TRETRY = 10b2
OCP_TRETRY = 11b4
VOLAOpen load active mode150300450mV
td(OL)Open load diagnostic delay timeOL_DLY = 0b0.3ms
OL_DLY = 1b1.2
IOLOpen load current3mA
TOTWThermal warning temperatureDie temperature (TJ)140150160°C
TTSDThermal shutdown temperatureDie Temperature (TJ)165175185°C
ThysThermal shutdown hysteresisDie temperature (TJ)20°C
(1) SDO output current external to the device
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