ZHCSIO5B October   2017  – January 2021 DRV8873-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control
        1. 7.3.1.1 Control Modes
        2. 7.3.1.2 Half-Bridge Operation
        3. 7.3.1.3 22
        4. 7.3.1.4 Internal Current Sense and Current Regulation
        5. 7.3.1.5 Slew-Rate Control
        6. 7.3.1.6 Dead Time
        7. 7.3.1.7 Propagation Delay
        8. 7.3.1.8 nFAULT Pin
        9. 7.3.1.9 nSLEEP as SDO Reference
      2. 7.3.2 Motor Driver Protection Circuits
        1. 7.3.2.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.2.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.2.3 Overcurrent Protection (OCP)
          1. 7.3.2.3.1 Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.2.3.2 Automatic Retry (OCP_MODE = 01b)
          3. 7.3.2.3.3 Report Only (OCP_MODE = 10b)
          4. 7.3.2.3.4 Disabled (OCP_MODE = 11b)
        4. 7.3.2.4 Open-Load Detection (OLD)
          1. 7.3.2.4.1 Open-Load Detection in Passive Mode (OLP)
          2. 7.3.2.4.2 Open-Load Detection in Active Mode (OLA)
        5. 7.3.2.5 Thermal Shutdown (TSD)
          1. 7.3.2.5.1 Latched Shutdown (TSD_MODE = 0b)
          2. 7.3.2.5.2 Automatic Recovery (TSD_MODE = 1b)
        6. 7.3.2.6 Thermal Warning (OTW)
      3. 7.3.3 Hardware Interface
        1. 7.3.3.1 MODE (Tri-Level Input)
        2. 7.3.3.2 Slew Rate
    4. 7.4 Device Functional Modes
      1. 7.4.1 Motor Driver Functional Modes
        1. 7.4.1.1 Sleep Mode (nSLEEP = 0)
        2. 7.4.1.2 Disable Mode (nSLEEP = 1, DISABLE = 1)
        3. 7.4.1.3 Operating Mode (nSLEEP = 1, DISABLE = 0)
        4. 7.4.1.4 nSLEEP Reset Pulse
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI) Communication
        1. 7.5.1.1 SPI Format
        2. 7.5.1.2 SPI for a Single Slave Device
        3. 7.5.1.3 SPI for Multiple Slave Devices in Parallel Configuration
        4. 7.5.1.4 SPI for Multiple Slave Devices in Daisy Chain Configuration
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Motor Voltage
        2. 8.2.1.2 Drive Current and Power Dissipation
        3. 8.2.1.3 Sense Resistor
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Thermal Considerations
        2. 8.2.2.2 Heatsinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.1.5 Slew-Rate Control

The rise and fall times (tr and tf) of the outputs can be adjusted on the hardware version of the device by changing the value of an external resistor connected from the SR pin to ground. On the SPI version of the device, the slew rate can be adjusted through the SPI. The output slew rate is adjusted internally to the device by controlling the ramp rate of the driven FET gate. The voltage or resistance on the SR pin sets the output rise and fall times in the hardware version of the device.

Table 7-10 DRV8873H-Q1 Slew Rate (SR) Pin Connections
CONNECTIONSRCIRCUIT
Connect to GND53.2 V/µsGUID-25C270CC-B0F4-467D-B16D-42EF622936E8-low.gif
22 kΩ ± 5% to GND34 V/µsGUID-3CFBB7C4-92F2-438D-B578-E28CED004DC5-low.gif
68 kΩ ± 5% to GND18.3 V/µsGUID-3CFBB7C4-92F2-438D-B578-E28CED004DC5-low.gif
> 2 MΩ to GND (Hi-Z)13 V/µsGUID-34B8E0AE-1E80-4983-8C56-EC3821AB8ACB-low.gif
51 kΩ ± 5% to DVDD7.9 V/µsGUID-F0E25417-64FD-4049-BBEB-1C1896BAFBBA-low.gif
Connect to DVDD2.6 V/µsGUID-CDD8DEDA-07D8-453A-AA71-F6ECD534B3BB-low.gif

Figure 7-8 shows the internal circuit block for the SR pin.

GUID-180D4A9E-746F-42EB-A89A-D5425119B629-low.gifFigure 7-8 SR Block Diagram

Table 7-11 lists the settings in the SPI register that set the output rise and fall times in the SPI version of the device.

Table 7-11 DRV8873S-Q1 Slew Rate Settings
SRRISE TIME (V/µs)FALL TIME (V/µs)
000b53.253.2
001b3434
010b18.318.3
011b1313
100b10.810.8
101b7.97.9
110b5.35.3
111b2.62.6

The typical voltage on the SR pin is 3 V and is driven internally. Changing the resistor value on the SR pin changes the slew-rate setting from approximately 2.6 V/µs to 53.2 V/µs. The recommended values for the external resistor are shown in the Section 7.3.3.2 section. If the SR pin is grounded then the slew rate is 53.2 V/µs. Leaving the SR pin as a no-connect pin sets the slew rate to 13 V/µs. Tying it to the DVDD pin sets the slew rate to 2.6 V/µs.
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