7.3.1 Motor Driver Current Ratings

Brushed motor drivers can be classified using two different numbers to describe the output current: peak and rms. Stepper motor drivers can be described with three numbers: peak, rms, and full-scale.

7.3.1.3 Full-Scale Current Rating

The full-scale current for a stepper motor describes the top of the sinusoid current waveform while stepping. Since the sineusoid amplitude is related to the rms current, the full-scale current is also determined by the thermal considerations of the IC. The full-scale current rating is approximately √2 × I_rms. The full-scale current is set by xVREF, the sense resistor, and Torque DAC when configuring the DRV8881. For the DRV8881, the full-scale current rating is 2.0 A per bridge.

Figure 13. Full-Scale and rms Current

7.3.2 PWM Motor Drivers

The DRV8881 contains drivers for two full H-bridges. Figure 14 shows a block diagram of the circuitry.

Figure 14. PWM Motor Driver Block Diagram

7.3.3 Bridge Control

The DRV8881E is controlled using a PH/EN interface. Table 1 gives the full H-bridge state. Note that this table does not take into account the current control built into the DRV8881E. Positive current is defined in the direction of xOUT1 → xOUT2.

The DRV8881P is controlled using a PWM interface. Table 2 gives the full H-bridge state. Note that this table does not take into account the current control built into the DRV8881P. Positive current is defined in the direction of xOUT1 → xOUT2.

7.3.4 Current Regulation

The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage, inductance of the winding, and the magnitude of the back EMF present. Once the current hits the current chopping threshold, the bridge enters a decay mode for a fixed period of time to decrease the current, which is configurable between 10 and 30 µs through the tri-level input TOFF. After the off time expires, the bridge is re-enabled, starting another PWM cycle.

The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pin with a reference voltage. To generate the reference voltage for the current chopping comparator, the xVREF input is attenuated by a factor of Av. In addition, the TRQx pins further scale the reference.

Figure 15. Current Regulation Block Diagram

The chopping current is calculated as follows:

Equation 1.

TRQ is a DAC used to scale the output current. The current scalar value for different inputs is shown in Table 4.

7.3.5 Decay Modes

A fixed decay mode is selected by setting the tri-level ADECAY and BDECAY pins as shown in Table 5. Note that if the ATE pin is logic high, the ADECAY and BDECAY pins are ignored and AutoTune is used.

The ADECAY pin sets the decay mode for H-bridge A (AOUT1, AOUT2), and the BDECAY pin sets the decay mode for H-bridge B (BOUT1, BOUT2).

7.3.5.1 Mode 1: Slow Decay

To configure the DRV8881 into this mode, pull DECAY1 and DECAY0 logic low.

Figure 16. Slow Decay Mode

During slow decay, both of the low-side FETs of the H-bridge are turned on, allowing the current to be recirculated.

Slow decay exhibits the least current ripple of the decay modes for a given t_OFF. However, if the current trip level is decreasing, slow decay will take a long time to settle to the new I_TRIP level because the current decreases very slowly.

7.3.5.2 Mode 2: Fast Decay

To configure the DRV8881 into this mode, pull DECAY1 and DECAY0 logic high.

Figure 17. Fast Decay Mode

During fast decay, the polarity of the H-bridge is reversed. The H-bridge will be turned off as current approaches zero in order to prevent current flow in the reverse direction.

Fast decay exhibits the highest current ripple of the decay modes for a given t_OFF. Transition time on decreasing current is much faster than slow decay since the current is allowed to decrease much faster.

7.3.5.3 Mode 3: 30%/70% Mixed Decay

To configure the DRV8881 into this mode, pull DECAY1 logic high and pull DECAY0 logic low.

Figure 18. Mixed Decay Mode (30% Fast, 70% Slow)

Mixed decay begins as fast decay for 30% of t_OFF, followed by slow decay for the remainder of t_OFF. In this mode, mixed decay occurs for both increasing and decreasing current steps.

This mode exhibits ripple larger than slow decay, but smaller than fast decay. Mixed decay will settle to the new I_TRIP level faster than slow decay when dealing with decreasing current trip levels.

In cases where current is held for a long time or at very-low stepping speeds, slow decay may not properly regulate current because no back-EMF is present across the motor windings. In this state, motor current can rise very quickly, and requires an excessively large off-time. Increasing/decreasing mixed decay mode allows the current level to stay in regulation when no back-EMF is present across the motor windings.

7.3.6 AutoTune

AutoTune is available on DRV8881E only.

To enable the AutoTune mode, pull the ATE pin logic high. Ensure the xDECAY pins are logic low. The AutoTune mode is registered internally when exiting from sleep mode or the power-up sequence. The ATE pin can be shorted to V3P3 to pull it logic high for this purpose.

AutoTune greatly simplifies the decay mode selection by automatically configuring the decay mode between slow, mixed, and fast decay. In mixed decay, AutoTune dynamically adjusts the fast decay percentage of the total mixed decay time. This feature eliminates motor tuning by automatically determining the best decay setting that results in the lowest ripple for the motor.

The decay mode setting is optimized iteratively each PWM cycle. If the motor current overshoots the target trip level, then the decay mode becomes more aggressive (add fast decay percentage) on the next cycle in order to prevent regulation loss. If there is a long drive time to reach the target trip level, the decay mode becomes less aggressive (remove fast decay percentage) on the next cycle in order to operate with less ripple and more efficiently.

AutoTune will automatically adjust the decay scheme based on operating factors like:

• Motor winding resistance and inductance
• Motor aging effects
• Motor dynamic speed and load
• Motor supply voltage variation
• Motor back-EMF difference on rising and falling steps
• Low-current vs. high-current dI/dt

7.3.7 Adaptive Blanking Time

After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a period of time before enabling the current sense circuitry. Note that the blanking time also sets the minimum drive time of the PWM.

The time t_BLANK is determined by VREF and the torque DAC setting. The timing information for t_BLANK is given in Table 6.

7.3.8 Parallel Mode

To enter parallel mode on the DRV8881P, the PARA pin must be logic high during device power-up or when exiting the sleep mode. The PARA pin can be shorted to V3P3 to pull it logic high for this purpose.

In this mode, the AIN1 and AIN2 pins control the state of the outputs and the BIN1 and BIN2 pins are ignored. Similarly, the ADECAY pin controls the decay mode of the output and AVREF is used as the analog reference voltage. The BIN1, BIN2, BDECAY, and BVREF pins can be tied to GND or left Hi-Z.

Figure 19. Parallel Mode Diagram

7.3.9 Charge Pump

A charge pump is integrated in order to supply a high-side NMOS gate drive voltage. The charge pump requires a capacitor between the VM and VCP pins. Additionally a low-ESR ceramic capacitor is required between pins CPH and CPL.

Figure 20. Charge Pump Diagram

7.3.10 LDO Voltage Regulator

An LDO regulator is integrated into the DRV8881. It can be used to provide the supply voltage for a low-power microcontroller or other low-current devices. For proper operation, bypass V3P3 to GND using a ceramic capacitor.

The V3P3 output is nominally 3.3 V. When the V3P3 LDO current load exceeds 10 mA, the LDO will behave like a constant current source. The output voltage will drop significantly with currents greater than 10 mA.

Figure 21. LDO Diagram

If a digital input needs to be tied permanently high (that is, TOFF or ADECAY), it is preferable to tie the input to V3P3 instead of an external regulator. This will save power when VM is not applied or in sleep mode: V3P3 is disabled and current will not be flowing through the input pulldown resistors. For reference, logic level inputs have a typical pulldown of 100 kΩ, and tri-level inputs have a typical pulldown of 40 kΩ.

7.3.11 Logic and Tri-Level Pin Diagrams

Figure 22 gives the input structure for logic-level pins APH/AIN1, AEN/AIN2, BPH/BIN1, BEN/BIN2, nSLEEP, ATE/PARA, TRQ0, TRQ1:

Figure 22. Logic-level Input Pin Diagram

Tri-level logic pins TOFF, ADECAY, and BDECAY have the following structure as shown in Figure 23.

Figure 23. Tri-Level Input Pin Diagram

7.3.12 Protection Circuits

The DRV8881 is fully protected against VM undervoltage, charge pump undervoltage, overcurrent, and overtemperature events.

Table 8. Functional Modes Summary