ZHCSFZ1A January 2017 – July 2018 DRV8886
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The DRV8886 device is active unless the nSLEEP pin is brought logic low. In sleep mode the charge pump is disabled, the H-bridge MOSFETs are disabled Hi-Z, and the regulators are disabled.
NOTE
The tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8886 device is brought out of sleep mode automatically if nSLEEP is brought logic high.
The tWAKE time must elapse before the outputs change state after wake-up.
TI recommends to keep the STEP pin logic low when coming out of nSLEEP or when applying power.
If the ENABLE pin is brought logic low, the H-bridge outputs are disabled, but the internal logic is still active. A rising edge on STEP advances the indexer, but the outputs do not change state until the ENABLE pin is asserted.
Table 9 lists a summary of the functional modes.
| CONDITION | H-BRIDGE | CHARGE PUMP | INDEXER | DVDD | AVDD | |
|---|---|---|---|---|---|---|
| Operating | 8 V < VM < 40 V
nSLEEP pin = 1 ENABLE pin = 1 |
Operating | Operating | Operating | Operating | Operating |
| Disabled | 8 V < VM < 40 V
nSLEEP pin = 1 ENABLE pin = 0 |
Disabled | Operating | Operating | Operating | Operating |
| Sleep mode | 8 V < VM < 40
nSLEEP pin = 0 |
Disabled | Disabled | Disabled | Disabled | Disabled |
| Fault encountered | VM undervoltage (UVLO) | Disabled | Disabled | Disabled | Operating | Disabled |
| VCP undervoltage (CPUV) | Disabled | Operating | Operating | Operating | Operating | |
| Overcurrent (OCP) | Disabled | Operating | Operating | Operating | Operating | |
| Thermal Shutdown (TSD) | Disabled | Operating | Operating | Operating | Operating | |