ZHCSJB5B September 2019 – December 2019 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The PWM generators are disabled to ensure that all the half-bridges are turned-on at same time to avoid false OCP conditions for supporting higher current operation. The false OCP condition can arise due to the minimum time required for the SPI delay to switch on various half-bridges available in different registers. This can cause higher current (OCP condition) in one of the paralleled half-bridge while other half-bridge turning ON is delayed to the SPI register write delay and the propagation delay. Therefore, this sequence includes disabling the PWM generators initially, then enabling half-bridges and followed by enabling the PWM generators to avoid such issue. The PWM generator-4 is disabled by using the following command in the PWM_CTRL_X registers:
NOTE
All PWM generators are enabled by default (Default value of PWM_CTRL_X registers is 00h).