8.3.3.3 Logic Supply Power on Reset (POR)

If at any time the input logic supply voltage on the VDD pin falls below the V_POR threshold or the nSLEEP pin is toggled (high to low), all of the half-bridges are disabled and the charge pump is disabled, as shown in Figure 51. Normal operation resumes (driver operation) when the VDD undervoltage condition is removed or the nSLEEP pin is latched high. The NPOR bit is reset and latched low in the IC status (IC_STAT) register once the device presumes VDD. The NPOR bit remains in reset condition until cleared through the CLR_FLT bit.

If the device has successfully waked up, then the NPOR bit is automatically latched high once the CLR_FLT command is issued.

Figure 51. VDD UVLO Operation