8.3.3.5.3 Passive OLD

In passive OLD, the detection of open load is carried before the driver is turned on. The state of all FETs remains in Hi-Z state, while a minimal amount of current flows through motor for short amount of time to test the motor connection. The diagnostic current is very small to avoid causing the motor rotation.

Figure 60 shows the circuit implementation of the passive OLD. As shown in this figure, a constant current source pulls the OUT1 pin to the AVDD (internal) fixed voltage which allows current flow from OUT1 to OUT2 terminal. The current drawn is completely dependent on the motor resistance between OUT1 and OUT2 and limited by the internal current sourcing (I_{OL_PU}) and sinking (I_{OL_PD}) capability of the passive OLD circuitry. Depending on this current and the comparator threshold voltage (V_{OL_HS} and V_{OL_LS}), the comparator output OL1_HS and OL2_LS are either set or reset which determines the open-load status. When an open load is detected, the OLD bit in the IC status (IC_STAT) register is set, the HBX_LS_OLD bit in the open-load status register (OLD_STAT_X) is set and nFAULT pin is driven low. The OLD bit remains set until cleared through the CLR_FLT bit. This implementation is applicable for any half-bridges.

Figure 60. Passive OLD Circuit

Following are the steps to configure and detect the passive OLD in the DRV89XX-Q1 device.

1. Enable the passive OLD mode for the individual half-bridges which is to be diagnosed using the Half-bridge passive OLD enable bits (HBX_POLD_EN) in OLD_CTRL_5 register.
2. Configure the half-bridge operation control bits (HBX_HS_EN/HBX_LS_EN) in operation control register (OP_CTRL_X) to determine the high-side and low-side OLD check. Note that these bits are now used for the passive OLD configuration. If anytime, the HBX_POLD_EN is reset then the bridge starts operating.
3. Enable the passive OLD using the Passive OLD Enable bit (POLD_EN) in CONFIG_CTRL register. Setting the POLD_EN bit enables the passive OLD detection circuit on all OUTx pin for which the corresponding HBX_HS_EN or HBX_LS_EN are set to 1.
4. Wait for the passive OLD time as determined by the user.
5. After the completion of passive OLD time, disable the passive OLD enable bit (POLD_EN).
6. Monitor the nFAULT pin / OLD bit in Status register (IC_STAT) and the HBX_HS_OLD/HBX_LS_OLD bit in the OLD status registers (OLD_STAT_X) for any open-load detection.
7. Restart the sequence for other half-bridges / full-bridges.

During normal driving, HBX_HS_EN and HBX_LS_EN bits control the state of OUTX. However, when POLD_EN and HBX_POLD_EN are 1, the OUTX channel is disabled, and HBX_HS_EN and HBX_LS_EN control SWX_HS and SWX_LS used for passive OLD (see schematic representation in Figure 60). Table 9 shows the truth table for this operation.

Table 10 shows an example for configuring passive OLD for various loads. The HBX_VM_POLD bits can be enabled for any loads that connect directly to VM. In cases where VM is low, the passive OLD current may need to be larger so passive OLD does not falsely indicate an open load. Setting HBX_VM_POLD = 1 chooses a smaller R_OL so more current flows and the device can properly detect an open load.