10.1 Layout Guidelines

The high speed inputs and outputs have been optimized to work with interconnects using a controlled differential impedance of 100Ω. Vias should be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias are used the layout must also provide for a low inductance path for the return currents as well. Route the differential signals away from other signals and noise sources on the printed circuit board.

The typical layout example Figure 13 highlights good high-speed layout techniques.

1. Maintain differential pair symmetry to minimize any signal conversion to common mode.
2. Isolate Tx - Rx differential pairs with a minimum of 5x inter-pair to intra-pair spacing ratio.
3. Decoupling should be placed as close as possible to the DS110DF111
4. Use differential vias which incorporate reference plane current returns and relief to minimize impedance disruption.
5. Use a back-drill technique to minimize via stubs.
6. Keep Loop Filter capacitors as close as possible to the DS110DF111.

10.2 Layout Example

Figure 13. DS110DF111 Typical Layout